3D Memory Seal Structure With Staggered Dummy Pillars

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing 3D memory devices face challenges in preventing external moisture and stress from affecting the chip array, and the manufacturing process is complex and costly.

Innovation Solution

A seal structure is designed with a dummy channel pillar array that penetrates through a ring-shaped stack structure, featuring staggered first and second dummy channel pillars to protect the chip array, and the formation process of these pillars is integrated with the channel pillar formation in the chip region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a seal structure is added to prevent external moisture and stress from affecting the chip array, then the reliability of the device is improved, but the device complexity increases

Engineering Contradiction:
Improveprotection against external moisture and stressVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dummy channel pillars are designed to serve dual purposes: they function as part of the seal structure to prevent external moisture and stress from reaching the chip array, while simultaneously being formed using the same manufacturing processes as the functional channel pillars. This multi-functionality approach allows the seal structure to provide protection without adding separate dedicated components, thereby improving reliability while minimizing the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention merges the seal structure formation with the existing channel pillar formation process. The dummy channel pillars are created using identical steps (patterning, etching, filling) as the functional channel pillars, combining two functions (sealing and data storage) into a unified structure. This integration allows the seal function to be achieved without adding separate manufacturing sequences, thus improving protection while keeping the overall device complexity manageable.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If a dummy channel pillar array is formed to protect the chip array, then the reliability is improved, but the manufacturing process becomes more complex and costly

Engineering Contradiction:
Improveprotection against external moisture and stressVSAvoidmanufacturing process complexity and cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The manufacturing process for dummy channel pillars is completely merged with the functional channel pillar formation process. Both types of pillars undergo the same patterning, etching, and filling steps in sequence without requiring separate manufacturing lines or additional process equipment. This merging approach allows the seal structure to be produced using existing manufacturing capabilities, improving reliability while avoiding increases in manufacturing complexity and cost.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The same manufacturing process equipment and materials are used to create both functional and dummy channel pillars, making the manufacturing system universal. The process steps (patterning with photoresist, etching through insulation layers, filling with conductive or insulating material) are identical for both pillar types, allowing the seal function to be achieved without requiring additional manufacturing resources or increasing production costs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If first and second dummy channel pillars are staggered to enhance protection, then the reliability is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improveprotection effectivenessVSAvoidpillar arrangement precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The dummy channel pillar array is segmented into two distinct groups: first dummy channel pillars and second dummy channel pillars with different patterns. The first group has pillars arranged at specific positions, while the second group has pillars arranged in a staggered pattern at offset positions. This segmentation allows each group to be formed with standard precision requirements, while the combined staggered arrangement achieves enhanced protection effectiveness without requiring ultra-high precision in any single patterning step.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The staggered arrangement of dummy channel pillars introduces a spatial dimension variation in the pillar distribution pattern. By alternating between two different pillar position patterns (first and second groups), the structure achieves three-dimensional-like protection coverage from a two-dimensional substrate, enhancing reliability while maintaining manufacturable precision levels through repeated use of standard patterning processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12469799B23D memory device and method of forming seal structure
Publication Date: 2025.11.11 MACRONIX INTERNATIONAL CO LTD
  • US12469799B2 patent drawing
  • US12469799B2 patent drawing
  • US12469799B2 patent drawing

AI summary

The present disclosure provides a 3D memory device such as a 3D AND flash memory and a method of forming a seal structure. The 3D memory device includes a chip region including a chip array and a seal region including a seal structure. The seal structure includes a ring-shaped stack structure disposed on a substrate and surrounding the chip array and a dummy channel pillar array penetrating through the ring-shaped stack structure and including a first dummy channel pillar group and a second dummy channel pillar group. The first dummy channel pillar group includes first dummy pillars that are arranged in a first direction and a second direction crossing the first direction to surround the chip array. The second dummy channel pillar group includes second dummy pillars that are arranged in the first direction and the second direction to surround the chip array. The first and the second dummy channel pillars are staggered with each other in the first and second directions.