3D Memory Vertical Channel Stack with Seed Layer Segmentation
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to the high cost of fine pattern forming technology, which restricts their ability to increase storage capacity and reduce production costs.
Innovation Solution
A three-dimensional semiconductor memory device with a vertical channel structure and a seed layer that includes alternating interlayer dielectric layers and gate electrodes, allowing for increased integration and improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited due to area constraints and high cost of fine pattern forming technology
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertical channel structures. The vertical channels extend in the depth direction (z-axis) through alternating stack structures, enabling data storage along the vertical dimension rather than only in the planar area, thereby dramatically increasing integration capacity while maintaining manufacturing feasibility
2Productivity
If fine pattern forming technology is advanced to increase integration, then storage capacity increases, but equipment cost increases extremely
Solution Approach 1:
Instead of increasing storage capacity by reducing feature size in the planar dimension (which requires expensive fine pattern forming equipment), the patent utilizes the vertical dimension with channel lengths extending several micrometers deep. This allows achieving high storage capacity with conventional lithography equipment, avoiding the need for extremely expensive advanced patterning tools
Solution Approach 2:
The patent employs nested alternating stack structures where first and second stack structures are vertically nested, with seed layers and charge trapping layers embedded within. This nested configuration enables high-density storage without requiring proportionally higher manufacturing complexity or equipment costs
3Productivity
If vertical channel structure with alternating stack structures is used, then integration and storage capacity increase, but process complexity increases
Solution Approach 1:
The patent divides the vertical channel structure into segmented alternating stacks - first stack structures and second stack structures separated by seed layers. Each stack contains specific functional layers (charge trapping layers, tunnel insulation layers, blocking insulation layers) that can be formed and processed independently, simplifying the overall manufacturing process while achieving high integration
4Manufacturing precision
If seed layer with spaced apart first and second seed patterns is used, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces seed layers as intermediary structures between the alternating stack structures and the vertical channel structures. The first seed patterns and second seed patterns are spaced apart in the horizontal direction, serving as mediators that define and control the formation of vertical channels and contact plugs, thereby improving manufacturing precision while the added structural complexity is managed through their simple horizontal spacing configuration
Data Source
AI summary
A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and including a first stack structure on the substrate and a second stack structure on the first stack structure, a seed layer interposed between the first and second stack structures and extended in a horizontal direction, vertical channel structures that penetrate the stack structure and are in contact with the substrate, and a first contact plug that penetrates the stack structure and is in contact with one of the gate electrodes. The seed layer may include first and second seed patterns enclosing the vertical channel structures and the first contact plug, and the first and second seed patterns may be spaced apart from each other in the horizontal direction.