3D Semiconductor Memory Device with Segmented Bit Lines
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Solution Overview
Problem
Current 3D semiconductor memory devices face challenges in achieving high integration density and reliability, which are crucial for reducing manufacturing costs and improving performance.
Innovation Solution
The design includes a 3D semiconductor memory device with vertically stacked cell strings and bit lines, where each cell string has a distinct number of string selection transistors with different threshold voltages, allowing for common bit line connection and selective electrical connection based on voltage conditions, enhancing integration density and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked cell strings are used to improve integration density, then the number of memory cells per unit area increases, but the complexity of electrical connection and control increases
Solution Approach 1:
The bit line is divided into multiple segments, with each segment connected to a specific cell string. This segmentation allows independent control of each cell string while sharing the bit line infrastructure, reducing the complexity of electrical connections compared to fully independent bit lines for each cell string.
Solution Approach 2:
The bit line serves multiple functions by being commonly connected to multiple cell strings. This multi-functionality reduces the total number of bit lines required, thereby improving integration density while managing electrical connection complexity through shared infrastructure.
2Measurement precision
If multiple string selection transistors are used for selective cell string access, then operational precision improves, but the number of transistors and device complexity increases
Solution Approach 1:
Different cell strings are equipped with different numbers of string selection transistors based on their specific access requirements. This local differentiation allows precise control where needed while minimizing transistor count in other areas, balancing operational precision with device complexity.
Solution Approach 2:
String selection transistors are positioned at strategic locations within the cell string structure to pre-establish control points. This preliminary placement of transistors enables selective access to cell strings before data operations occur, improving precision while optimizing the number of transistors required.
3Adaptability or versatility
If cell strings with different numbers of string selection transistors are implemented, then operational flexibility improves, but manufacturing precision requirements increase
Solution Approach 1:
The array of cell strings is segmented into groups with different numbers of string selection transistors. This segmentation into standardized groups simplifies manufacturing by creating repeatable patterns, reducing the precision requirements compared to completely custom configurations for each cell string.
Solution Approach 2:
The number of string selection transistors is varied as a design parameter across different cell string groups to achieve operational flexibility. By treating this as a controllable parameter rather than a fixed value, the design accommodates manufacturing variations while maintaining the intended flexibility benefits.
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode.