3D Semiconductor Memory Devices With Segmented Vertical Channels
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density while minimizing the cost and complexity of fine pattern production, particularly in transitioning from two-dimensional to three-dimensional arrangements.
Innovation Solution
A three-dimensional semiconductor memory device design featuring common source regions, vertically stacked electrodes, and channel structures with specific insulation layers and impurity layers, allowing for efficient electrical connections and data storage, while minimizing leakage current and fabrication defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with word lines, bit lines, and channel structures arranged in multiple levels. This dimensional change dramatically increases integration density without requiring proportionally finer lateral patterning, thus improving storage capacity while managing manufacturing complexity.
2Manufacturing precision
If fine patterns are produced to increase integration, then manufacturing cost increases, but integration density improves
Solution Approach 1:
By stacking memory cell layers vertically, the patent achieves higher integration density without proportionally increasing lateral patterning fineness. The vertical stacking allows multiple cells to share common source and drain regions, reducing the number of separate patterning steps required compared to lateral expansion with fine patterns.
Solution Approach 2:
Common source regions and common drain regions are shared by multiple memory cell strings in the vertical stack. These common regions serve multiple functions: providing electrical connections for multiple cells, reducing the number of individual source/drain structures needed, and simplifying the overall manufacturing process by reducing pattern complexity.
3Manufacturing precision
If vertically stacked electrodes are implemented, then integration density improves, but leakage current risk increases
Solution Approach 1:
The vertical channel structures are segmented into discrete sections by insulation layers positioned between adjacent memory cell layers. These insulation layers electrically isolate different segments of the channel, preventing leakage current from propagating vertically between stacked cells. The segmentation maintains the benefits of vertical stacking while addressing reliability concerns.
Solution Approach 2:
Insulation layers are introduced as intermediary structures between adjacent memory cell layers and channel structures. These layers act as electrical barriers that prevent direct current leakage between stacked cells while maintaining the vertical integration architecture. The insulation layers mediate between the need for high-density vertical stacking and the requirement for electrical isolation.
4Device complexity
If common source regions are shared, then device complexity reduces, but electrical isolation becomes more difficult
Solution Approach 1:
While common source regions are shared horizontally among multiple memory cell strings, the vertical channel structures are segmented by insulation layers at each memory cell layer interface. This segmentation ensures electrical isolation between vertically stacked cells even though they share common source regions, maintaining both structural simplification and electrical reliability.
Data Source
AI summary
A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.