3D Memory Gate Electrode Uniformity via Segmented Contact Holes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in 3D memory device fabrication lies in the difficulty of forming uniform gate electrodes due to large gate line slits and varying channel hole dimensions, leading to non-uniform threshold voltages and increased resistance, as well as wafer warpage issues affecting photolithography and die yield.
Innovation Solution
The introduction of contact hole structures with insulating spacers and conductive contacts, uniformly distributed among memory strings, replaces traditional gate line slits, allowing for improved uniformity of gate electrodes and threshold voltages, and reduces warpage bias by minimizing lateral distances for conductive material deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional gate line slits are used in 3D memory device fabrication, then the fabrication process is simpler, but the gate electrodes become non-uniform and resistance increases
Solution Approach 1:
The gate line slit is segmented into multiple contact hole structures distributed among memory strings. Each contact hole structure includes an insulating spacer and conductive contact, replacing the continuous gate line slit with discrete, uniformly distributed elements that improve gate electrode uniformity while maintaining fabrication feasibility
Solution Approach 2:
The contact hole structures are selectively positioned among specific memory strings with uniform lateral distances, creating localized uniformity in the gate electrode formation process. This local quality approach ensures consistent threshold voltages and reduces resistance variations in critical regions
2Ease of manufacture
If gate line slits are used, then fabrication is easier, but threshold voltage uniformity deteriorates
Solution Approach 1:
The gate line slit is divided into multiple discrete contact hole structures distributed among memory strings. This segmentation allows for more precise control of conductive material deposition and ensures uniform threshold voltages across different memory strings while maintaining fabrication simplicity
Solution Approach 2:
The contact hole structures are arranged with uniform lateral distances among surrounding memory strings, creating equipotential conditions for conductive material deposition. This arrangement ensures that all memory strings experience similar electrical conditions, resulting in uniform threshold voltages
3Ease of manufacture
If large gate line slits are used, then fabrication is simpler, but wafer warpage increases affecting photolithography
Solution Approach 1:
The large gate line slit is segmented into multiple smaller contact hole structures distributed among memory strings. This segmentation reduces the overall lateral extent of the conductive material deposition process, minimizing stress accumulation and wafer warpage that would otherwise affect photolithography alignment
Solution Approach 2:
The gate line slit is transformed from a continuous lateral structure into discrete vertical contact hole structures. This dimensional change from a planar continuous structure to a distributed three-dimensional structure reduces the lateral footprint and minimizes wafer warpage while maintaining electrical connectivity
4Ease of manufacture
If varying channel hole dimensions are present, then fabrication is easier, but gate electrode uniformity worsens
Solution Approach 1:
The contact hole structures are selectively positioned among memory strings with controlled local dimensions. By ensuring uniform lateral distances from contact holes to surrounding channel structures, the invention achieves local uniformity in gate electrode formation even when overall device dimensions vary
Solution Approach 2:
The invention changes the critical parameter from varying channel hole dimensions to uniform lateral distances from contact holes to channel structures. This parameter transformation allows for easier fabrication while maintaining gate electrode uniformity through controlled spatial relationships rather than precise dimensional control
Data Source
AI summary
Embodiments of a three-dimensional (3D) memory device are provided. A method for forming a 3D memory device is disclosed. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed over a substrate. Channel holes and contact holes are formed through the dielectric stack. The contact holes extend vertically into the substrate and are each surrounded by channel holes of nominally equal lateral distances to the respective contact hole in a plan view. A channel structure is formed in each of the channel holes. A memory stack having interleaved conductive layers and dielectric layers is formed by replacing, through the contact holes, the sacrificial layers in the dielectric stack with the conductive layers. A spacer is formed along a sidewall of each of the contact holes to cover the conductive layers of the memory stack. A contact is formed over the spacer in each of the contact holes. The contact is electrically connected to a common source of the channel structures.