3D Nonvolatile Memory Integration via Segmented Hole Architecture
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Solution Overview
Problem
Conventional 3D nonvolatile memory devices face limitations in increasing integration degree due to the restricted size of holes formed during the mask and etch process, which limits the number of channels and subsequently the number of memory cells that can be formed.
Innovation Solution
A nonvolatile memory device is fabricated with a stacked structure featuring interlayer dielectric and conductive layers, where holes are formed to expose the substrate, and the memory and channel layers are separated into multiple parts within each hole, allowing for increased integration by forming multiple memory cells within the same area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the hole width is reduced to increase the number of memory cells, then the integration degree is improved, but the manufacturing precision deteriorates due to exposure limits during mask and etch processes
Solution Approach 1:
The patent divides a single hole into multiple sub-regions by forming partitions within the hole. This segmentation allows multiple memory cells to be formed within the same hole area, increasing the number of memory cells without reducing the overall hole width, thereby avoiding exposure limitations while achieving higher integration density
Solution Approach 2:
The patent transitions from a 2D planar arrangement of memory cells to a 3D vertical stacking structure. By forming memory cells in multiple layers within the same hole footprint, the device achieves higher integration density without reducing the lateral dimensions of individual holes, thus avoiding exposure process limitations
2Quantity of substance
If the number of channels is increased to improve integration degree, then the number of memory cells increases, but the device complexity increases due to additional mask and etch processes
Solution Approach 1:
The patent combines multiple channel formation operations into a single etch process by using a unified mask pattern that defines all channel locations simultaneously. This merging approach increases the number of channels while avoiding the need for multiple sequential mask and etch processes, thereby reducing fabrication complexity
Solution Approach 2:
The mask pattern serves multiple functions: it defines hole locations, defines channel locations within holes, and defines partition structures. This multi-functionality allows the same masking step to enable increased channel density without proportionally increasing process complexity
Data Source
AI summary
A nonvolatile memory device includes a stacked structure disposed over a substrate and having a plurality of interlayer dielectric layers and conductive layers that are alternately stacked, a plurality of holes formed to pass through the stacked structure to expose the substrate, a first memory layer and a second memory layer formed separately in a circumference of each hole, and a first channel layer and a second channel layer formed respectively on the first and second memory layers.