3D Memory Structure Fabrication via Segmented Active Stacks
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Solution Overview
Problem
The challenge in fabricating three-dimensional NOR-type memory strings is the difficulty in anisotropically etching narrow trenches all the way down to the bottommost active layer, especially in tall vertical stacks, which can lead to incomplete etching and mechanical instability.
Innovation Solution
The method involves forming multiple active stack sections separated by dielectric buffer layers, where each active stack section includes trenches filled with sacrificial material. After forming multiple active stack sections, the sacrificial material is removed, and portions of the dielectric buffer layer are removed between adjacent active stack sections. This process reduces the aspect ratio for anisotropic etching and allows for the formation of local word line structures with a gate dielectric layer and conductor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If tall vertical stacks of active layers are formed to increase memory capacity, then storage capacity is improved, but the aspect ratio for trench etching increases making complete etching difficult and mechanically unstable
Solution Approach 1:
The patent divides the tall vertical stack into multiple segments called active stack sections, separated by dielectric buffer layers. Each section contains a subset of active layers (e.g., 4-8 layers per section), which reduces the etching depth required for each segment while maintaining the overall high-capacity structure through vertical stacking of multiple sections.
2Manufacturing precision
If multiple charge-storage layer formation steps are performed for each active layer, then local word line structures are formed, but thermal budget increases causing dopant out-diffusion
Solution Approach 1:
The patent merges the charge-storage layer formation process into a single step that processes all active stack sections simultaneously. Instead of performing separate charge-storage layer formation for each active layer, the method forms charge-storage layers in all sections together using one thermal cycle, thereby reducing total thermal exposure and preventing dopant out-diffusion while still achieving complete local word line structure formation.
Data Source
AI summary
A method for forming a three-dimensional memory structure above a semiconductor substrate includes forming two or more active stack sections, each formed on top of each other and separated by a dielectric buffer layer, where each active stack section includes multilayers separated by isolation dielectric layers and trenches with shafts filled with a sacrificial material. After the multiple active stack sections are formed, the method removes the sacrificial material in the shafts and removes portions of the dielectric buffer layer between shafts of adjacent active stack sections. The method fills the openings with a gate dielectric layer and a gate conductor. In some embodiments, the gate dielectric layer is discontinuous in the shaft over the depth of the multiple active stack sections.