3D Memory Devices With Segmented Word Lines
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving high device density and performance due to limitations in the design of memory arrays and transistors.
Innovation Solution
The development of three-dimensional memory arrays with transistors featuring three-dimensional channel regions, formed by word lines with main and projecting portions, and film stacks deposited along these structures, allowing for improved transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three-dimensional channel regions are formed using word lines with main and projecting portions, then transistor performance is improved through increased electric field and better on-off current ratios, but device structure and manufacturing process become more complex
Solution Approach 1:
The word line is segmented into a main portion and multiple projecting portions that extend into trenches. This segmentation allows the electric field to be concentrated in specific regions where the projecting portions contact the semiconductor layers, improving transistor performance while maintaining a manageable structural complexity through systematic repetition of the projecting portions.
Solution Approach 2:
The word line structure transitions from a traditional planar two-dimensional configuration to a three-dimensional structure with projecting portions extending vertically into trenches. This dimensional change enables the gate to exert stronger control over the channel by establishing electric fields in multiple spatial dimensions, thereby improving transistor reliability.
2Quantity of substance
If memory arrays are designed with higher device density, then storage capacity increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The structure employs a nested configuration where projecting portions of the word line are positioned within trenches that contain semiconductor layers. This nesting arrangement maximizes the use of vertical space, allowing multiple functional regions to be packed into a compact volume, thereby increasing device density while maintaining manufacturability through standardized trench formation processes.
Data Source
AI summary
In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.