3D Memory Select Channel Structure for Programming Voltage Control
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Solution Overview
Problem
The challenge in three-dimensional memory devices is to enhance storage density and electron transfer efficiency while minimizing interference during programming operations, particularly due to the introduction of channel plugs which can affect programming voltage distribution.
Innovation Solution
The solution involves forming a three-dimensional memory device with a select channel structure that includes a block layer and a second channel layer, where the conductive layer contacts the block layer, and a channel plug connects the first and second channel layers, allowing direct contact and improving programming efficiency by avoiding the need for channel plugs that can cause interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional stacked layers and channel structures are used, then device structure is simpler, but electron transfer efficiency and control capabilities are insufficient
Solution Approach 1:
The channel structure is segmented into multiple distinct layers including a first channel layer, block layer, second channel layer, and optional third channel layer. Each layer serves specific functional purposes: first and second channel layers for electron transfer, block layer for controlling electron flow. This segmentation enables independent optimization of each layer's properties to enhance overall electron transfer efficiency while maintaining precise control capabilities.
Solution Approach 2:
Different materials and structures are applied to different regions of the channel. The block layer uses specific materials (such as silicon oxynitride) with distinct electrical properties from the channel layers. The conductive layer is selectively positioned to contact specific portions of the block layer. This local differentiation of material properties and structures allows optimized electron transfer in channel regions while maintaining control in block regions.
2Quantity of substance
If storage density is increased through more stacked layers, then storage capacity improves, but control capabilities of top select gate transistors deteriorate
Solution Approach 1:
The channel structure extends in multiple dimensions with vertical stacking of channel layers and horizontal extension of the conductive layer. The conductive layer wraps around or contacts the block layer from multiple directions, providing control from additional spatial dimensions. This multi-dimensional control architecture maintains effective transistor control even as the number of stacked layers increases for higher storage density.
Solution Approach 2:
The channel layers are nested within dielectric materials, and the conductive layer is nested to contact the block layer which itself is nested within the channel structure. The dielectric core is positioned within the channel layers. This nested arrangement allows compact integration of multiple functional elements, enabling increased storage density through vertical stacking while maintaining control capabilities through the nested conductive-block-channel structure.
Data Source
AI summary
The present disclosure provides a three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device comprises: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers and comprising a conductive layer sandwiched between two dielectric layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer.