3D Memory Select Circuit with Level Shifters
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving high-speed operation and increased storage density while minimizing space for peripheral circuitry, particularly in three-dimensional memory arrays where column address changes during programming can delay the process and require extensive global routing lines, leading to increased capacitance and resistance.
Innovation Solution
A monolithic three-dimensional memory array design that includes selective connection of bit lines to sense amplifiers using selection circuits with level shifters, allowing for pipelined programming without changing column addresses, and utilizing global column decoders to reduce space and enhance programming speed, along with a capacitive discharge method to prevent unwanted current flow through memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If column address changes during programming in three-dimensional memory arrays, then programming flexibility is improved, but programming speed deteriorates and process delays occur
Solution Approach 1:
The patent applies preliminary action by pre-selecting all required columns using a global column decoder before the programming operation begins. The column selection is performed in advance and remains fixed throughout the programming process, eliminating the need to change column addresses during programming. This allows programming to proceed at maximum speed without interruption, while still maintaining the ability to select any column combination through the initial decoding phase.
2Adaptability or versatility
If extensive global routing lines are used to connect bit lines to sense amplifiers, then connectivity is improved, but parasitic capacitance and resistance increase
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple blocks, each with its own local sense amplifiers and column decoders. Instead of routing all bit lines globally to a single sense amplifier bank, each block handles its own bit lines locally. This segmentation reduces the length and number of global routing lines, thereby reducing parasitic capacitance and resistance while maintaining full connectivity through the distributed architecture.
Solution Approach 2:
The patent introduces a block dimension to the memory architecture, organizing memory cells into three-dimensional blocks rather than a single planar array. This dimensional organization allows bit lines to be grouped and handled within each block, reducing the need for long global routing lines that would span the entire chip. The block structure provides a natural hierarchy that reduces parasitic effects while maintaining connectivity.
3Productivity
If more space is allocated for peripheral circuitry to support high-speed operation, then programming speed is improved, but storage density deteriorates
Solution Approach 1:
The patent merges the column decoder functionality into the block structure itself, rather than having separate decoder circuits outside the memory array. The global column decoder is integrated with the block organization, and local column decoders are incorporated within each block. This merging eliminates the need for extensive external peripheral circuitry, allowing high-speed operation to be achieved while maximizing the use of chip area for storage cells rather than support circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases programming speed, reduces space requirements for semiconductor die, and minimizes parasitic capacitance, enabling efficient high-speed operation and high storage density without the need for frequent column address changes, thus improving overall memory performance.
Implementation Method 1
a capacitive discharge method to prevent unwanted current flow through memory cells
Data Source
AI summary
A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.