3D Memory Select Gate Structure for Higher Cell Current
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Solution Overview
Problem
The existing semiconductor storage devices with three-dimensional memory cell arrays face challenges due to narrow channel widths of select gates, which limit cell current, and off-leakage currents due to uncontrolled voltage in semiconductor regions without gate electrodes.
Innovation Solution
The semiconductor storage device incorporates a structure with first and second columnar bodies within a stacked body, featuring conductive and insulating films alternately stacked, and a gate electrode film that is thicker than the conductive films in the channel direction, ensuring adequate cell current and preventing off-leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode is provided around the columnar semiconductor region, then the select gate structure is formed, but the channel width becomes narrow which limits cell current
Solution Approach 1:
The patent transitions from a planar gate electrode configuration to a three-dimensional stacked structure with multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) arranged vertically. This dimensional change allows the gate to control the channel from multiple levels, effectively increasing the control area without proportionally increasing the channel width constraint, thus resolving the contradiction between gate control reliability and cell current limitation.
Solution Approach 2:
The gate electrode is divided into multiple segmented components (first gate electrode, second gate electrode, third gate electrode) stacked in different layers. Each gate electrode segment controls a specific portion of the channel, allowing distributed control that maintains effective channel width while achieving comprehensive gate coverage. This segmentation enables the channel current to flow through multiple parallel paths around the columnar semiconductor region.
2Reliability
If the gate electrode is provided around the columnar semiconductor region, then the select gate structure is formed, but off-leakage current occurs due to uncontrolled voltage in semiconductor regions without gate electrode
Solution Approach 1:
By stacking gate electrodes in the vertical dimension (first gate electrode in first layer, second gate electrode in second layer, third gate electrode in third layer), the patent achieves comprehensive three-dimensional coverage of the columnar semiconductor region. This multi-layer configuration ensures that all semiconductor regions are under gate control, eliminating uncontrolled voltage zones that would generate off-leakage current while maintaining the select gate's reliable control function.
Solution Approach 2:
The multiple gate electrodes are nested around the central columnar semiconductor region in a concentric arrangement, with each gate electrode layer surrounding the columnar region. This nested configuration ensures complete coverage of the semiconductor region from multiple vertical levels, preventing any uncontrolled voltage zones and eliminating the source of off-leakage current while preserving the select gate's control reliability.
Data Source
AI summary
A semiconductor storage device includes a first stacked body including first insulating films and first conductive films that are alternately stacked in a first direction. A first columnar body and a second columnar body extend within the first stacked body in the first direction. A second conductive film is provided above the first stacked body, and extends in a third direction intersecting the first direction and the second direction. A third insulator is adjacent to the second conductive film and extends in the third direction. A third conductive film is adjacent to the third insulator and extends in the third direction. A third columnar body is provided on the first columnar body. A fourth columnar body is provided on the second columnar body. A thickness of a third semiconductor portion in the first direction is greater than a thickness of the second conductive film in the first direction.