3D Memory Device Select Gate Layering for Leakage Reduction
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Solution Overview
Problem
Current memory cell technologies face challenges in achieving high density and reducing costs per bit, as critical dimensions shrink, leading to inefficiencies in storage capacity and energy loss due to leakage paths in traditional two-dimensional memory devices.
Innovation Solution
A three-dimensional memory device is developed with selectively formed select gates in different layers to reduce leakage paths and enhance energy efficiency, utilizing a 3D array structure with multiple vertically stacked memory layers and select gates formed in distinct metal layers, such as FinFETs or planar transistors, to control bit and select lines, thereby reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional two-dimensional memory devices are used, then manufacturing is simpler, but leakage paths increase causing energy loss
Solution Approach 1:
The patent transitions from traditional two-dimensional memory architecture to a three-dimensional structure by stacking multiple memory cell layers vertically. This dimensional change reduces leakage paths between selected and unselected rows by isolating them in different vertical layers, thereby reducing energy loss while managing the increased structural complexity through systematic layer stacking
2Quantity of substance
If critical dimensions are shrunk to increase density, then storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
Instead of continuing to shrink critical dimensions in the planar direction, the patent stacks multiple memory cell layers vertically to achieve higher storage capacity. This approach increases density by utilizing the vertical dimension while avoiding the need to further reduce already miniaturized critical dimensions, thus managing manufacturing precision requirements
3Loss of energy
If select gates are formed in the same layer as memory cells, then manufacturing is easier, but leakage current increases
Solution Approach 1:
The patent segments the select gates into separate vertical layers from the memory cells. By placing select gates in different layers than the memory cells they control, the structure isolates leakage paths and reduces interference between selected and unselected rows. This segmentation increases manufacturing complexity but effectively reduces leakage current
4Quantity of substance
If multiple memory layers are stacked vertically, then storage capacity increases, but device complexity increases
Solution Approach 1:
The patent implements vertical stacking of multiple memory cell layers to achieve higher storage capacity in a compact footprint. This three-dimensional arrangement increases density by utilizing the vertical dimension while managing the inherent structural complexity through systematic layer stacking and integration of select gates in separate layers
Data Source
AI summary
A memory device includes a three dimensional memory array having memory cells arranged on multiple floors in rows and columns. Each column is associated with a bit line and a select line. The memory device further includes select gate pairs each being associated with a column. The bit line of a column is connectable to a corresponding a global bit line through a first select gate of a select gate pair associated with the column and a select line of the column is connectable to a corresponding global select line through the second select gate of the select gate pair associated with the column. The plurality of select gate pairs are formed in a different layer than the plurality of memory cells.