3D Memory Select-Gate Layout With Isolated Groups and Vertical Contacts
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Solution Overview
Problem
Current semiconductor memory devices face challenges in simplifying the manufacturing process while maintaining the complexity of three-dimensional memory cell arrangements, which affects the integration density and efficiency of memory cells within a limited area.
Innovation Solution
The semiconductor memory device incorporates a specific structure with a first and second select group isolated by an isolation insulating layer, featuring an upper gate stack structure with alternately stacked conductive and interlayer insulating patterns, channel structures penetrating these groups, and a vertical connection structure with contact patterns extending from the isolation layer, simplifying the manufacturing process by using a slit forming and contact hole filling method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell arrangements are implemented to improve integration density, then the integration density of memory cells is improved, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming isolation insulating layers between select groups, creating slit patterns, and filling contact holes. This segmentation allows complex 3D structures to be built through manageable sequential steps rather than attempting to create the entire structure at once.
Solution Approach 2:
The patent transitions from two-dimensional planar manufacturing to three-dimensional vertical structures by forming stacked gate patterns and contact holes that extend through multiple layers. This enables higher integration density by utilizing the vertical dimension for additional memory cells while maintaining a compact footprint.
2Quantity of substance
If isolation insulating layers are formed between select groups to enable three-dimensional arrangement, then memory cell integration is improved, but the manufacturing steps increase
Solution Approach 1:
The isolation insulating layer formation is merged with the gate pattern formation process. The same lithography and etching steps that create the gate structures also define the isolation regions, eliminating the need for separate isolation processing steps and maintaining manufacturing efficiency.
Solution Approach 2:
The slit patterns serve multiple functions: they define the gate structure geometry, establish the contact hole positions, and create the isolation regions. This multi-functionality reduces the total number of processing steps required while achieving the desired three-dimensional memory cell integration.
3Productivity
If vertical connection structures with contact patterns are used to connect memory cells, then the three-dimensional arrangement efficiency is improved, but the contact hole formation complexity increases
Solution Approach 1:
The contact hole positions are predetermined by the slit pattern formation step. The slits are etched to specific geometries that automatically define where contact holes will be formed, ensuring precise alignment with the gate structures and select groups before the contact hole filling process begins.
Solution Approach 2:
The slit patterns act as an intermediary structure that bridges the gate patterns and the contact holes. They provide a template that guides the subsequent contact hole formation process, ensuring that contacts are precisely positioned to connect the vertical connection structures to the appropriate memory cell components.
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.