3D Memory Drain Select Gates With Self-Aligned Isolation Spacers
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming self-aligned multi-level drain select level gate electrodes, which are crucial for enhancing memory density and performance, due to limitations in manufacturing processes that affect the precision and isolation of conductive layers and dielectric structures.
Innovation Solution
The proposed solution involves forming a three-dimensional memory device with an alternating stack of insulating and conductive layers over a substrate, where memory stack structures extend through the stack with vertical semiconductor channels, and employing a method that includes forming sacrificial spacers and replacing sacrificial material layers with conductive connectors, along with a drain select level isolation dielectric structure to create self-aligned conductive structures, enabling precise electrical connections and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing processes are used to form drain select level gate electrodes, then the manufacturing process is simpler, but the alignment precision and isolation of conductive layers deteriorate
Solution Approach 1:
Sacrificial material layers are formed at predetermined locations before the actual conductive layers are deposited. These sacrificial layers serve as temporary placeholders that guide the subsequent formation of drain select level gate electrodes, ensuring precise self-alignment without requiring complex lithography steps. The sacrificial spacers are also formed in advance to define the exact positions where conductive connectors will be placed.
Solution Approach 2:
Sacrificial material layers and sacrificial spacers act as intermediary elements that facilitate the precise formation of conductive structures. These temporary structures mediate between the manufacturing process and the final device structure, enabling accurate alignment of conductive layers with dielectric structures. After serving their alignment function, the sacrificial materials are removed, leaving behind precisely positioned conductive elements.
2Reliability
If dielectric structures occupy larger volume for isolation, then the isolation of conductive elements is improved, but the memory device density deteriorates
Solution Approach 1:
The patent employs thin dielectric films and spacer structures to achieve effective electrical isolation between conductive elements. Instead of using bulky dielectric blocks, thin dielectric layers are deposited conformally on the sidewalls of conductive structures, providing sufficient isolation while occupying minimal volume. This approach maintains reliable electrical isolation while preserving memory device density.
Solution Approach 2:
The isolation function is transitioned from a three-dimensional bulky dielectric structure to a two-dimensional thin film approach. Dielectric materials are applied as thin conformal coatings on the sidewalls of conductive elements rather than as large volume blocks, achieving effective electrical isolation through surface coverage rather than volume occupation. This dimensional transition significantly reduces the space required for isolation while maintaining reliability.
Data Source
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AI summary
Sacrificial memory opening fill structures are formed through an alternating stack of insulating layers and sacrificial material layers. A drain select level isolation trench extending through drain select level sacrificial material layers is formed employing a combination of a photoresist layer including a linear opening and a pair of rows of sacrificial memory opening fill structures as an etch mask. Sacrificial spacers are formed on sidewalls of the drain select level isolation trench. A drain select level isolation dielectric structure is formed in a remaining volume of the drain select level isolation trench. The sacrificial memory opening fill structures are replaced with memory stack structures. The sacrificial material layers and the sacrificial spacers are replaced with a conductive material to form electrically conductive layers and conductive connector spacers. The drain select level isolation dielectric structure is self-aligned to the memory stack structures and divides drain select level electrically conductive layers.