3D Memory Common Select-Line Layout for Area-Efficient Ferroelectric Cells
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Solution Overview
Problem
Existing memory devices face challenges in balancing speed and data retention, with volatile memory devices losing data upon power loss and non-volatile devices being slower, necessitating improved 3D memory systems that enhance memory area efficiency and reduce fabrication costs.
Innovation Solution
A 3D memory system is developed with ferroelectric memory cells arranged in multiple tiers, sharing select lines between transistor structures, utilizing ferroelectric materials for data storage and employing a method that includes forming trenches, depositing layers, and etching sacrificial layers to create a memory array with shared conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory devices are used to retain data without power, then data retention is improved, but access speed deteriorates
Solution Approach 1:
The memory system is divided into multiple tiers with different memory types (ferroelectric memory cells in first tier, second memory cells in second tier). Each tier handles different aspects of data storage, allowing the system to provide both fast access (first tier) and non-volatile retention (second tier), thus resolving the contradiction between speed and data retention.
Solution Approach 2:
The patent transitions from traditional planar memory architecture to a three-dimensional stacked architecture with multiple tiers. This vertical dimension allows different memory types to coexist and operate simultaneously, enabling fast ferroelectric memory to handle read operations while slower non-volatile memory provides backup storage, thereby achieving both speed and retention.
2Area of stationary object
If select lines are shared between transistor structures, then memory area efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of separate select lines by implementing shared select lines that serve multiple transistor structures across different tiers. This consolidation reduces the total number of select lines needed, improving memory area efficiency while the systematic sharing approach manages the complexity through regularized connection patterns.
Solution Approach 2:
Select lines are designed with multi-functionality to serve multiple purposes: they control transistor structures in different tiers, handle both read and write operations, and provide common control signals across the memory array. This universal design reduces the overall number of control lines needed, improving area efficiency despite increased individual line complexity.
Data Source
AI summary
One aspect of this description relates to a semiconductor device. In some embodiments, the semiconductor device includes a first drain/source structure extending in a first direction, a second drain/source structure extending the first direction and spaced from the first drain/source structure in a second direction perpendicular to the first direction, a third drain/source structure extending in the first direction and spaced from the second drain/source structure in the second direction, a first bit line disposed over the first drain/source structure in the first direction, a common select line that includes a portion disposed over the second drain/source structure in the first direction, a second bit line disposed over the third drain/source structure in the first direction, and a charge storage layer coupled to at least a first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure.