3D Memory Array Select Lines for Parallel Sum-of-Products
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current neuromorphic computing and machine learning systems face challenges in efficiently performing high-speed sum-of-products operations due to the need for large arrays that can execute many operations in parallel, which is not adequately addressed by existing circuitry.
Innovation Solution
A 3D array of cells is designed with a column of memory cells formed using pillars and vertical conductive lines, incorporating pillar select switches and bottom select lines to apply bias voltages and currents independently, enabling efficient execution of sum-of-products operations in a large array configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large array is used to execute many operations in parallel, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from a conventional 2D cross-point array to a 3D array architecture by adding vertical conductive lines and multiple levels of word lines. This dimensional expansion enables significantly more memory cells to be packed into a given footprint, allowing for large-scale parallel operations without proportionally increasing the planar device footprint, thus improving productivity while managing device complexity through vertical integration.
Solution Approach 2:
The patent divides the large array into multiple independent columns, each with its own pillar select switch and bottom select line. This segmentation allows for independent control and operation of different column segments, enabling parallel processing across multiple columns while keeping each individual column's control logic manageable, thus resolving the contradiction between large-scale parallel operations and control complexity.
2Measurement precision
If independent bias voltage control is implemented for vertical semiconductor bodies, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces pillar select switches as intermediary components between the bottom select lines and the vertical semiconductor bodies. These switches act as controlled access points that enable independent bias voltage application to specific columns while maintaining a relatively simple overall structure. The intermediary switches provide precise control without requiring complex direct connection schemes to each semiconductor body.
Solution Approach 2:
The patent implements dynamic control capabilities through the pillar select switches and bottom select lines, allowing the bias voltage configuration to be changed on-the-fly for different operational modes (read, program, erase). This dynamic reconfigurability enables precise bias control for different measurement and operation requirements without permanently complicating the physical structure, as the complexity is managed through time-multiplexed control signals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the efficient execution of sum-of-products operations in large arrays, enhancing the performance of neuromorphic computing and machine learning systems by enabling parallel processing and precise control of bias voltages and currents.
Implementation Method 1
a gate dielectric between the pillar select line and the vertical semiconductor body
Implementation Method 2
The bottom select line is in current-flow contact with the vertical semiconductor body of the pillar
Data Source
AI summary
A device comprises a column of cells disposed in multiple levels of word lines including a pillar comprising a first vertical conductive line, a second vertical conductive line, and a vertical semiconductor body disposed between and in contact with the first and second vertical conductive lines. A pillar select line is adjacent to and separated by a gate dielectric from the vertical semiconductor body to form a pillar select switch, the pillar select line disposed beneath the first and second vertical conductive lines. A bottom select line is disposed beneath the first and second vertical conductive lines and insulated from the pillar select line and the first and second vertical conductive lines. The bottom select line is in current-flow contact with the vertical semiconductor body of the pillar.