3D Nonvolatile Memory Selection Transistors with Vertical Stacking
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Solution Overview
Problem
Conventional 3D nonvolatile memory devices face limitations in integration density due to large area occupation by flat drain selection transistors, high likelihood of leakage current, and increased fabrication costs associated with multiple mask layers, along with resistance limitations in polysilicon-based drain selection lines.
Innovation Solution
The solution involves forming channel structures with interlayer dielectric layers, channel contacts, and vertically-coupled selection lines made of low-resistance materials, with a gate all around (GAA) selection transistor structure and a silicon gate electrode to prevent direct contact with the gate dielectric layer, reducing area, leakage, and resistance while simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flat drain selection transistors are formed on channel layers, then selection transistor functionality is achieved, but area occupation increases and integration density is limited
Solution Approach 1:
The patent transitions from planar 2D transistors to vertically stacked 3D transistors, utilizing the vertical dimension to achieve higher integration density. Multiple channel layers are stacked vertically with selection lines extending through them, allowing more transistors to be packed into the same footprint area while maintaining full selection transistor functionality.
2Reliability
If flat drain selection transistors are formed, then selection transistor functionality is achieved, but leakage current increases
Solution Approach 1:
The vertical stacking configuration improves the on/off ratio by creating better channel control through the stacked structure. The selection lines pass through multiple channel layers in the vertical direction, enabling more effective electrostatic control and reducing off-state leakage current compared to planar configurations.
Solution Approach 2:
The patent implements nested structures where gate electrodes and channel layers are interleaved in a stacked configuration. Each selection line is nested within the vertical stack, surrounded by multiple channel layers, which enhances the control efficiency and reduces leakage through improved field confinement.
3Ease of manufacture
If polysilicon-based drain selection lines are used, then fabrication is simplified, but resistance is high
Solution Approach 1:
The patent employs composite material structures for selection lines, combining polysilicon with metal layers or using metal silicide materials. This composite approach maintains the ease of fabrication associated with polysilicon processes while significantly reducing the resistance through the addition of highly conductive metal components.
4Manufacturing precision
If multiple mask layers are used for forming drain selection lines, then precise patterning is achieved, but fabrication cost and complexity increase
Solution Approach 1:
The patent merges the formation of multiple drain selection lines into a single patterning step using a common mask layer. The selection lines are formed simultaneously at different vertical levels through a unified process, eliminating the need for separate mask and etch steps for each line, thereby reducing fabrication complexity while maintaining precise patterning.
Data Source
AI summary
A 3D nonvolatile memory device includes a plurality of channel structures each comprising a plurality of channel layers and interlayer dielectric layers which are alternately stacked, a plurality of channel contacts coupled to the plurality of channel layers, respectively, and a plurality of selection lines vertically-coupled to the plurality of channel contacts and crossing over the plurality of channel structures.