3D Memory Stack Fabrication with Selective Deposition Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and improving manufacturing productivity.
Innovation Solution
The method involves forming three-dimensionally arranged memory cells by alternately stacking sacrificial layers and interlayer insulating layers, patterning to create a stepped structure, and forming deposition inhibition and selective deposition layers to construct gate electrodes and isolation openings, enhancing the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are formed by alternately stacking sacrificial layers and interlayer insulating layers, then data storage capacity is increased, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple functional components: sacrificial layers for defining memory cell regions, interlayer insulating layers for electrical isolation, channel structures for data storage, and gate electrodes for control. This segmentation allows complex three-dimensional memory structures to be built from simpler repeating units, increasing storage capacity while managing complexity through modular design
Solution Approach 2:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. By stacking sacrificial layers and interlayer insulating layers alternately in the vertical direction, the memory device achieves higher data storage capacity within the same footprint area, effectively utilizing the third dimension to resolve the contradiction between storage capacity and device footprint
2Manufacturing precision
If patterned sacrificial layers and patterned interlayer insulating layers are formed with stepped structure, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Sacrificial layers are formed and patterned in advance before the final memory structure is complete. These preliminary structures serve as templates that guide subsequent deposition and patterning steps, ensuring precise alignment and positioning of channel structures and gate electrodes. The stepped structure of patterned layers provides predetermined alignment references that improve manufacturing precision while the sacrificial nature allows removal after serving their guiding function
Solution Approach 2:
The patterned sacrificial layers and interlayer insulating layers act as intermediary structures during manufacturing. These intermediate layers facilitate precise positioning and alignment of subsequent structures through their stepped configuration, then are removed after serving their purpose. The intermediaries enable high precision manufacturing without permanently increasing device complexity
3Manufacturing precision
If deposition inhibition layers and selective deposition layers are formed on exposed surfaces, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
Deposition inhibition layers are applied selectively only to exposed surfaces of patterned interlayer insulating layers, while selective deposition layers are formed only on exposed surfaces of patterned sacrificial layers. This local application of different deposition treatments to specific regions ensures precise control over material placement and prevents unwanted deposition, improving manufacturing precision without requiring complete reprocessing of entire wafers, thus maintaining productivity
4Manufacturing precision
If channel structures and isolation openings are formed by removing sacrificial layers, then manufacturing precision is improved, but loss of substance increases
Solution Approach 1:
Sacrificial layers are removed after serving their purpose as templates for defining memory cell regions and guiding structure formation. The removal process creates precise isolation openings and defines channel structure positions with high manufacturing precision. While the sacrificial material is discarded, the process enables precise formation of functional structures without requiring continuous presence of the sacrificial layers, accepting material loss as necessary for achieving the desired precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases data storage capacity and improves manufacturing efficiency by enabling the formation of complex semiconductor structures with enhanced productivity.
Implementation Method 1
forming deposition inhibition layers on exposed surfaces of the patterned interlayer insulating layers
Implementation Method 2
forming selective deposition layers on exposed surfaces of the patterned sacrificial layers
Data Source
AI summary
A method of manufacturing a semiconductor device is provided including the operations of forming a peripheral circuit structure including a substrate, circuit elements on the substrate, and interconnections on the circuit elements. The method includes forming a plate layer on the peripheral circuit structure, forming a preliminary stack structure by alternately stacking sacrificial layers and interlayer insulating layers on the plate layer in a first direction perpendicular to an upper surface of the plate layer, and patterning the stack structure to form a stepped structure to form patterned sacrificial layers and patterned interlayer insulating layers. The method includes forming deposition inhibition layers on exposed surfaces of the patterned interlayer insulating layers, forming selective deposition layers on exposed surfaces of the patterned sacrificial layers, forming channel structures penetrating through the preliminary stack structure in the first direction, and contacting the plate layer.