3D Memory Structure With Self-Aligned Control Lines and Fewer Masks
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Solution Overview
Problem
The increasing cost of mask sets and low flexibility in semiconductor manufacturing pose challenges, especially for custom products, due to the need for multiple expensive mask sets to accommodate varying designs and higher data transfer rates, which are not efficiently addressed by existing 3D stacked integrated circuits and borderless logic arrays.
Innovation Solution
The development of 3D semiconductor memory devices with self-aligned control lines and oxide layers, utilizing Through-Silicon-Via connections and thin film transistors for programming circuits, allows for reduced mask costs and increased flexibility by enabling modular construction of configurable logic, memory, and I/O dies, with antifuse programming transistors placed above or below the interconnect circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple custom mask sets are used to accommodate varying designs, then design flexibility is improved, but manufacturing cost increases exponentially
Solution Approach 1:
The patent implements a universal mask set that can accommodate multiple custom designs through programmable logic arrays and configurable interconnect circuits. The same physical mask structure serves multiple design functions by allowing different logic configurations and interconnect patterns to be programmed into the generic array structure, eliminating the need for separate custom masks for each design.
Solution Approach 2:
The device is divided into modular components including generic logic arrays, configurable interconnect circuits, and programmable regions. This segmentation allows the same mask set to produce different functional configurations by programming different segments of the array, providing design flexibility without requiring multiple complete mask sets.
2Adaptability or versatility
If dedicated mask sets are created for each custom product, then product customization is improved, but development cost increases
Solution Approach 1:
Instead of creating physical copies of mask sets for each custom product, the patent uses a single master mask set that defines a generic array structure. Custom products are achieved by programming different logic functions and interconnect patterns into this generic structure, creating virtual copies of customized devices from a single physical mask master.
3Quantity of substance
If 3D stacked integrated circuits are used to increase density, then device density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functional layers (logic arrays, interconnect circuits, programming circuits) into a single integrated 3D stacked structure. By combining these functions in vertical layers with through-silicon via connections, the device achieves high density while using a unified manufacturing process that reduces overall complexity compared to separate fabrication of multiple components.
Data Source
AI summary
A 3D semiconductor memory, the memory including: a first level including first memory cells, first transistors, and a first control line, where the first memory cells each include one of the first transistors; a second level including second memory cells, second transistors, and a second control line, where the second memory cells each include one of the second transistors, where the second level overlays the first level, where the second control line and the first control line have been processed following the same lithography step and accordingly are self-aligned, where the first control line is directly connected to each source or drain of at least five of the first transistors, and where the second control line is directly connected to each source or drain of at least five of the second transistors; and an oxide layer disposed between the first control line and the second control line.