3D Memory Vertical Array Sense Amplifier Segmentation
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Solution Overview
Problem
In 3D memory devices, the limited number of sense amplifiers for vertical array cores leads to diluted access and reduced refresh performance, limiting the operation of memory cells and increasing system overhead.
Innovation Solution
Implementing an additional set of sense amplifiers with their own access path to service vertical array stacks, along with multiplexing devices to switch between them for efficient data access and refresh operations, and integrating a hierarchical digitline architecture with built-in SRAM cache to reduce the need for external caches and enhance bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged vertically in 3D configuration to reduce component size, then memory density is improved, but sense amplifier availability per array core is reduced
Solution Approach 1:
The patent divides the memory system into multiple independent array cores, each with its own dedicated sense amplifier. This segmentation ensures that sense amplifiers are not shared across multiple vertical array cores, thereby maintaining full availability and performance for each core while enabling high-density 3D vertical stacking.
Solution Approach 2:
The patent transitions from a 2D planar memory architecture to a 3D vertical stacking architecture. By arranging memory cells vertically in multiple stacked layers, the system achieves higher memory density without compromising sense amplifier availability, as each vertical array core maintains its own dedicated sense amplifier in the 3D space.
2Device complexity
If standard sense amplifiers service multiple vertical array cores, then device complexity is reduced, but refresh performance and access speed are degraded
Solution Approach 1:
The patent segments the memory system into independent array cores with dedicated sense amplifiers, eliminating the need for sense amplifiers to service multiple vertical array cores. This segmentation improves refresh performance and access speed by ensuring that each sense amplifier has exclusive access to its associated array core, avoiding performance degradation from shared resources.
3Ease of manufacture
If vertical array stacking is implemented for die size scaling, then manufacturing cost is reduced, but sense amplifier dilution occurs
Solution Approach 1:
The patent implements segmentation by creating multiple independent array cores, each with its own dedicated sense amplifier. This approach enables die size scaling through vertical stacking while preventing sense amplifier dilution, as each sense amplifier remains fully effective for its associated core without being shared across multiple cores.
Solution Approach 2:
The patent utilizes 3D vertical stacking to achieve die size scaling while maintaining sense amplifier effectiveness. By organizing memory cells in vertical layers with dedicated sense amplifiers for each array core, the system scales efficiently in the vertical dimension without suffering from sense amplifier dilution that would occur in shared configurations.
Data Source
AI summary
Systems and methods using a three-dimensional memory device with a number of memory cells disposed vertically in a number of pillars arranged along a horizontal direction can be used in a variety of applications. In various embodiments, pillars of memory cells may be disposed between lower and upper digitlines respectively coupled to different sense amplifiers to provide read/write operations and refresh operations. In various embodiments, a three-dimensional memory device having an array of memory cells vertically arranged in pillars may include a sense amplifier and digitline with a static random access memory cache, where the static random access memory cache is disposed below the array of memory cells in the same die. Additional apparatus, systems, and methods are disclosed.