3D Memory Stack with Separate Program and Erase Paths
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Solution Overview
Problem
The integration density of two-dimensional non-volatile memory devices is limited, necessitating the development of three-dimensional structures, but existing three-dimensional non-volatile memory devices face challenges in operational reliability and efficiency due to shared paths for program/read and erase operations.
Innovation Solution
A semiconductor device with a stack structure featuring separate paths for program/read and erase operations, utilizing a source plate and well plate electrically insulated from each other, and connection structures that pass through the stack structure to facilitate independent bias application, improving operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional non-volatile memory devices are developed to improve integration density, then integration density is improved, but operational reliability deteriorates due to shared paths for program/read and erase operations
Solution Approach 1:
The patent divides the memory device into separate functional paths: a first path for program and read operations, and a second path for erase operations. This segmentation is achieved by providing separate well plates (first and second well plates) and associated connection structures, allowing independent operation of different memory functions without interference, thereby resolving the reliability issue while maintaining the 3D vertical structure for high integration density
2Device complexity
If shared paths are used for program/read and erase operations to simplify device structure, then device complexity is reduced, but operational efficiency deteriorates due to interference between operations
Solution Approach 1:
The patent implements separate first and second paths for different operations, with dedicated well plates and connection structures for each path. This allows program/read operations to proceed simultaneously and independently from erase operations, eliminating mutual interference and improving operational efficiency while maintaining manageable device complexity through systematic structural organization
3Productivity
If separate paths for program/read and erase operations are implemented to improve operational efficiency, then operational efficiency is improved, but device complexity increases due to additional connection structures
Solution Approach 1:
The patent utilizes the vertical dimension of the 3D stack structure to accommodate multiple well plates and connection structures at different height levels. By stacking memory cells vertically and providing connection structures that extend through multiple layers, the patent implements separate operational paths without significantly increasing the horizontal footprint, thereby managing device complexity while achieving improved operational efficiency
Data Source
AI summary
A semiconductor device includes a stack structure, a channel layer passing through the stack structure, a memory layer enclosing the channel layer and including first and second openings which expose the channel layer, a well plate coupled to the channel layer through the first opening, and a source plate coupled to the channel layer through the second opening.