3D Memory Cell Layout With Separated Contacts for Higher Density
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and integration density.
Innovation Solution
A semiconductor device with a three-dimensional arrangement of memory cells, featuring stacked gate electrodes, channel structures, contact plugs, and separation regions that enhance integration by optimizing the layout and electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged two-dimensionally, then the device structure is simple, but the data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking of gate electrodes and channel structures. Multiple gate electrodes (first, second, third gate electrodes) are stacked vertically to form memory cells in the third dimension, thereby increasing data storage capacity without proportionally increasing footprint area.
Solution Approach 2:
The memory device is segmented into multiple functional regions including first memory cell region, second memory cell region, third memory cell region, and peripheral circuit region. Each region contains specifically arranged gate electrodes and channel structures, allowing independent optimization and integration of different functional blocks.
2Productivity
If gate electrodes are stacked vertically to increase integration, then the degree of integration improves, but the manufacturing precision requirements increase
Solution Approach 1:
Insulating layers are introduced as intermediary structures between stacked gate electrodes to provide electrical isolation and mechanical support. The insulating layers act as mediators that enable precise positioning and alignment of multiple gate electrodes during manufacturing processes.
Solution Approach 2:
Different regions of the device employ different gate electrode configurations and stacking arrangements optimized for their specific functions. Memory cell regions use vertical stacking for high density, while peripheral circuit regions use planar arrangements for ease of manufacturing and electrical performance.
3Productivity
If contact plugs are arranged densely to improve integration, then the degree of integration improves, but the reliability of electrical connections deteriorates
Solution Approach 1:
Contact plugs are extracted and separately positioned in specific regions (first contact plug region, second contact plug region) rather than being uniformly distributed. This separation allows optimized routing and connection schemes for different gate electrode layers, improving connection reliability while maintaining integration.
Solution Approach 2:
Contact plugs extend in the vertical direction to connect with stacked gate electrodes at multiple levels. This three-dimensional contact plug arrangement enables reliable electrical connections through the vertically stacked structure without requiring excessive lateral density.
4Reliability
If separation regions are added to isolate gate electrodes, then the reliability improves, but the device complexity increases
Solution Approach 1:
Separation regions are merged with insulating layers and interlayer structures to provide both electrical isolation and mechanical support functions simultaneously. This integration reduces the need for additional separate isolation structures, maintaining reliability while controlling device complexity.
Solution Approach 2:
The insulating layers serve multiple functions: electrical isolation between gate electrodes, mechanical support for vertical stacking, and structural definition for contact plug formation. This multi-functionality reduces overall device complexity while maintaining reliable electrical isolation.
Data Source
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AI summary
A semiconductor device (100) according to example embodiments of the present disclosure includes: a plate layer, gate electrodes (130) stacked and spaced apart from each other and including lower gate electrodes, memory gate electrodes, and upper gate electrodes, channel structures (CH) extending through the gate electrodes (130), first contact plugs (MC1) electrically connected to the upper gate electrodes, respectively, second contact plugs (MC2) extending through portions of the gate electrodes (130) and electrically connected to the memory gate electrodes and the lower gate electrodes, respectively, gate separation regions (MS) extending through the gate electrodes (130), and first upper separation regions (SS1) extending through the upper gate electrodes between the gate separation regions (MS). Each of the first contact plugs (MC1) may be in contact with at least one of the first upper separation regions (SS1), and the second contact plugs (MC2) may be spaced apart from the first upper separation regions (SS 1).