3D Memory Stack Layout With Separation Pattern for Dense NAND
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high data storage capacity and reliability while maintaining integration density.
Innovation Solution
The semiconductor device incorporates a stack structure with vertically stacked electrodes, string selection lines, upper and lower vertical structures, and an upper separation pattern, designed to enhance electrical connectivity and reduce patterning complexity, thereby improving integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking of memory cells. Multiple layers of memory cells are stacked vertically with word lines and bit lines extending through the stack, enabling significantly increased storage capacity by utilizing the third dimension (height) rather than only expanding in the plane.
Solution Approach 2:
The three-dimensional memory structure is divided into multiple functional segments including word lines, bit lines, select lines, and memory cell layers. Each segment performs a specific function and can be independently controlled, allowing complex 3D operations to be broken down into manageable discrete actions that simplify the overall system control.
2Quantity of substance
If integration density is increased through vertical stacking, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning actions where string selection lines and separation patterns are formed before the final memory cell structures. The upper separation pattern is positioned between string selection lines in advance, establishing a framework that guides subsequent fabrication steps and ensures precise alignment of vertically stacked components.
Solution Approach 2:
The upper separation pattern serves as an intermediary structure between the string selection lines and the vertically stacked memory cells. This intermediate element facilitates precise positioning and alignment of the stacked structures, acting as a reference or guide that enables high integration density without requiring extreme manufacturing precision throughout the entire process.
3Speed
If string selection lines are added for vertical memory access, then data access speed is improved, but device complexity increases
Solution Approach 1:
The selection mechanism is segmented into multiple independent select lines (first string selection line, second string selection line, first select line, second select line) that can be activated independently. Each select line controls access to specific regions or layers of the vertical memory stack, enabling parallel access operations and reducing the complexity of any single selection operation.
Solution Approach 2:
Data access transitions from planar two-dimensional addressing to three-dimensional vertical addressing by introducing string selection lines that extend vertically through multiple memory cell layers. This enables direct access to specific layers without scanning through intermediate layers, significantly improving access speed while the modular select line structure manages the increased complexity.
Data Source
AI summary
Disclosed are a semiconductor device and an electronic system including the same. The semiconductor device may include a stack on a substrate and extending in a first direction, the stack including electrodes vertically stacked on the substrate, string selection lines that are on the stack, extend parallel to the first direction, and are spaced apart from each other in a second direction crossing the first direction, an upper separation pattern that is on the stack, extends in the first direction, and is between the string selection lines, lower vertical structures in the stack, and upper vertical structures in the string selection lines and electrically connected to the lower vertical structures, respectively.