3D Memory SGD Stadium Layout for Dense Self-Supporting Arrays
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Solution Overview
Problem
Conventional memory devices face challenges in increasing memory density and reducing die size due to structural issues such as bending and cumbersome support features, particularly in the construction of drain-side-select-gate (SGD) transistors, which require complex layouts and elongation of SGD staircase structures.
Innovation Solution
The implementation of a pillar progression with a SGD stadium located within the pillar arrangement, providing self-support and optimizing area usage, along with conductive paths to control circuitry, reduces the risk of tier collapse and allows for dimension reduction of the SGD stadium, enabling more efficient signal routing and enhanced memory device design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional drain-side-select-gate (SGD) transistor structures are used, then memory devices can be fabricated with basic functionality, but the devices suffer from structural bending issues, cumbersome support features, and increased die size
Solution Approach 1:
The patent transitions from planar SGD transistor structures to a three-dimensional stacked architecture where memory cells are arranged in vertical tiers. The SGD stadium is positioned at a specific vertical level within the stack, allowing select gates to control multiple memory cell tiers simultaneously. This vertical integration reduces the horizontal footprint and die size while maintaining structural stability through the self-supporting pillar design.
Solution Approach 2:
The memory device is divided into discrete vertical pillars, each containing multiple tiers of memory cells. The SGD stadium is segmented into individual select gates that can independently control different tiers. This segmentation allows for modular construction, reducing overall die size while improving structural stability through distributed support pillars.
2Quantity of substance
If memory density is increased through conventional scaling, then more storage capacity is achieved, but structural bending and support complexity increase
Solution Approach 1:
The patent achieves increased memory density by stacking memory cell tiers vertically within pillars rather than expanding horizontally. Each pillar contains multiple tiers of memory cells separated by intervening regions, allowing high-density storage while maintaining structural stability through the vertical pillar architecture that naturally resists bending forces.
Solution Approach 2:
The design incorporates intervening regions between memory cell tiers that serve as cushioning spaces for stress relief and structural support. These regions prevent stress accumulation that could lead to structural bending, allowing high memory density to be achieved without compromising structural stability.
3Ease of operation
If SGD staircase structures are elongated to provide proper routing, then signal connectivity is improved, but device complexity and area increase
Solution Approach 1:
The patent simplifies signal routing by utilizing vertical conductive paths through the stacked architecture. SGD contacts are formed at the base level and extend vertically to connect to select gates at different tiers, eliminating the need for complex elongated staircase structures. This vertical routing approach reduces layout complexity while maintaining excellent signal connectivity.
Data Source
AI summary
A variety of applications can include apparatus having memory devices, where at least one of the memory devices is a three-dimensional memory device having levels of pillars to support pillars of memory cells and one or more drain-end select gate (SGD) transistors of the memory array of the memory device. The levels of pillars are structured as a progression of pillars, where each pillar of one level is structured on and extending vertically from a different pillar of a level on which the one level is located. SGD select lines for coupling to the one or more SGD transistors are structured in a SGD stadium, where the SGD stadium is located within at least a portion of the progression of pillars.