3D Semiconductor Memory Structure With Shared Bit Lines
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Solution Overview
Problem
Two-dimensional semiconductor structures, such as DRAM, face challenges in achieving high storage density and integration, which are insufficient for modern semiconductor storage capacity requirements.
Innovation Solution
A three-dimensional semiconductor structure is formed by stacking semiconductor layers with alternating sacrificial layers, forming horizontal capacitors, word lines, and vertical bit lines, allowing for increased integration and storage density, with transistors sharing a bit line to reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor structures are used, then manufacturing process is simple, but storage density and integration are low
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional stacked structures by forming multiple semiconductor layers stacked vertically. Each layer contains transistors and capacitors arranged in different spatial planes, enabling storage elements to be stacked in the vertical direction (third direction) while maintaining planar bit lines in the first direction, thereby significantly increasing storage density without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent implements nested structures where capacitors are formed within or alongside transistor structures across multiple stacked layers. The capacitor structures in lower layers are positioned to share vertical space with transistor structures in upper layers, creating a nested arrangement that maximizes space utilization and increases storage density within the same footprint area
2Quantity of substance
If more storage units are integrated, then storage capacity increases, but structure size increases
Solution Approach 1:
The patent stacks semiconductor layers in the vertical direction (third direction) to increase storage capacity without proportionally increasing the horizontal footprint. Multiple storage units are arranged in vertical columns where each layer contributes additional storage capacity while sharing the same planar area, thereby increasing storage density and reducing the overall structure size for a given storage capacity
Solution Approach 2:
The patent designs shared bit lines that extend through multiple stacked layers and serve multiple transistors across different layers. A single bit line can electrically connect to transistors in several stacked semiconductor layers, reducing the total number of bit lines required and minimizing the horizontal space needed for interconnect structures, thereby increasing storage capacity without proportionally increasing structure size
Data Source
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AI summary
This invention relates to a semiconductor structure and a method for forming the semiconductor structure. The method for forming a semiconductor structure includes the following steps: forming a stacking layer on a top surface of a substrate, where the stacking layer includes a plurality of semiconductor layers arranged at intervals in a first direction, and the stacking layer includes a transistor region, a capacitor region, and a bit line region, where the semiconductor layers include semiconductor columns arranged at intervals in a third direction; forming, in the capacitor region, a capacitor extending in the second direction; forming a word line in the transistor region, where the word line extends in the third direction and continuously covers the semiconductor columns arranged at intervals in the third direction; and forming a bit line in the bit line region, where the bit line extends in the first direction.