3D Memory Cell Structure With Shared Electrode for Higher Density
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) manufacturing while maintaining complexity and efficiency, requiring advancements in IC processing and manufacturing techniques to support the increasing density and complexity of ICs.
Innovation Solution
A method of forming a memory device involves creating a stack structure with dielectric and conductive layers, patterning to form through holes and recesses, depositing data storage material, and forming channel and gate pillar structures, which enables the fabrication of memory cells with improved density and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The fabrication process is divided into multiple distinct stages including forming insulating layers, forming sacrificial layers, forming recesses, filling recesses with conductive materials, and removing sacrificial layers. Each stage is independently optimized and controlled, allowing complex 3D structures to be built through sequential simpler operations rather than attempting to create them in a single step.
Solution Approach 2:
Sacrificial layers are deposited and patterned in advance before the final conductive structures are formed. These preliminary sacrificial structures serve as templates that guide subsequent material deposition and define the final geometry. The sacrificial layers are removed only after they have fulfilled their templating function, enabling precise control over the final structure formation.
2Quantity of substance
If functional density is increased while scaling down, then more devices per chip area are achieved, but manufacturing complexity increases
Solution Approach 1:
The structure employs nested layers where insulating layers contain sacrificial layers, which in turn define recesses that are filled with conductive materials. Each layer is embedded within and depends on the previous layer, creating a hierarchical structure that maximizes device density within the available chip area while maintaining manufacturability through standardized deposition and etching processes.
Solution Approach 2:
The fabrication process transitions from 2D planar structures to 3D vertical structures by forming recesses that extend through multiple layers and filling them with conductive materials. This vertical dimensionality increase allows more interconnects and devices to be packed into the same chip footprint, effectively increasing functional density without proportionally increasing manufacturing complexity.
Data Source
AI summary
A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.