3D Memory Cell Structure With Shared Electrode for IC Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) manufacturing processes while maintaining complexity and efficiency, which requires advancements in IC processing and manufacturing techniques.
Innovation Solution
The development of a method for forming a memory device that involves creating a stack structure with dielectric and conductive layers, patterning to form through holes and lateral recesses, depositing a data storage material, and forming channel and gate pillar structures within the through holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent transitions from planar 2D memory structures to three-dimensional vertically-stacked structures. Multiple memory layers are stacked vertically with alternating conductive and dielectric layers, enabling increased storage density without proportionally increasing footprint area. This vertical dimensionality change allows continued scaling benefits while managing processing complexity through standardized layer formation processes.
Solution Approach 2:
The patent implements nested structures where conductive layers are embedded within dielectric layers, and memory elements are nested within vertical stacks. The vertically-stacked architecture nests multiple functional layers (conductive, dielectric, memory) within each other, achieving high density by packing components in three dimensions rather than spreading them out in two dimensions.
2Quantity of substance
If functional density is increased by scaling down, then more devices fit per chip area, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory structure into repeating modular units consisting of conductive layers, dielectric layers, and memory elements arranged in vertical stacks. Each layer type can be formed using standardized deposition and patterning processes, allowing the structure to be scaled by simply adding more repeating units rather than redesigning the entire architecture.
Solution Approach 2:
The vertically-stacked design uses universal layer formation processes that can be applied repeatedly to create multiple memory layers. The same conductive and dielectric layer deposition techniques are used across all layers, and the structure supports both storage and control functions within the same physical footprint, improving manufacturing efficiency.
Data Source
AI summary
A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.