3D Memory Cell Array With Shared Interconnections
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in achieving higher density and cost reduction due to complexities in the three-dimensional memory structure, particularly in the peripheral circuit, which hinders the miniaturization of memory elements and increases production costs.
Innovation Solution
A semiconductor memory device with a three-dimensional memory cell array structure where memory cells are stacked with shared interconnections, allowing for vertical overlap and common connections between adjacent layers, reducing the complexity of the peripheral circuit and enabling cost-effective high-density memory integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arrayed with diodes or non-ohmic elements, then memory element density is improved, but peripheral circuit complexity increases
Solution Approach 1:
The patent merges the peripheral circuit functions into the memory block structure by sharing word lines and bit lines across multiple memory cell arrays. The interconnections are designed to serve multiple functions simultaneously, reducing the need for separate peripheral circuit components and achieving higher integration without increasing overall complexity.
Solution Approach 2:
The word lines and bit lines are designed as universal interconnections that can be shared by multiple memory cell arrays. Each interconnection serves multiple functions: acting as both word lines and bit lines for different arrays, enabling the same physical structure to support higher memory density without requiring additional dedicated peripheral circuitry.
2Ease of manufacture
If multi-layer NAND flash memory is used for cost reduction, then production cost is improved, but processing difficulty and field effect transistor limits worsen
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrays to three-dimensional stacked memory cell arrays. By stacking multiple memory cell arrays vertically and sharing interconnections between layers, the invention achieves higher integration density and cost-effectiveness while avoiding the processing difficulties and transistor scaling limits associated with conventional multi-layer NAND flash memory.
3Area of moving object
If chip-size reduction is pursued, then integration is improved, but peripheral circuit miniaturization becomes difficult
Solution Approach 1:
The patent implements a nested structure where memory cell arrays are stacked vertically with interconnections shared between layers. The peripheral circuit functions are nested within the memory block structure itself, with word lines and bit lines serving multiple arrays simultaneously. This nesting approach reduces the overall chip area by eliminating redundant peripheral circuit components and achieving higher integration density.
Data Source
AI summary
A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.