3D Memory Array Layout With Shared Bit-Line Penetrating Pillars
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Solution Overview
Problem
Existing 3D DRAM technologies face a bottleneck in improving storage density due to limitations in memory cell design and layout, particularly with the 1T1C architecture.
Innovation Solution
A three-dimensional memory array design with a stacked structure and penetrating pillars, where two memory cells are positioned opposite each other on either side of a pillar, sharing a bit line, and utilizing a symmetric structure to optimize space utilization and reduce cell size, incorporating a transistor and capacitor arrangement in a perpendicular direction to enhance storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If one memory cell is disposed per penetrating pillar in related technology, then the layout is simple, but the storage density is limited
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked structure, where memory cells are arranged vertically around penetrating pillars. This dimensional change allows multiple memory cells to be positioned at different heights and angular positions around each pillar, dramatically increasing storage density without proportionally increasing layout complexity
Solution Approach 2:
The patent divides the space around each penetrating pillar into multiple segments or sectors, with memory cells positioned at different angular positions (e.g., 0 degrees, 90 degrees, 180 degrees, 270 degrees). This segmentation allows multiple memory cells to share a single penetrating pillar while maintaining organized, manageable layouts
2Quantity of substance
If memory cell size is reduced to increase storage density, then more cells fit per layer, but manufacturing precision requirements increase
Solution Approach 1:
By moving to a three-dimensional stacked architecture, the patent increases storage capacity vertically rather than horizontally compressing cell sizes. This approach accommodates more memory cells per layer through vertical stacking and radial arrangement around pillars, avoiding the need to excessively reduce individual cell dimensions and thereby maintaining feasible manufacturing precision requirements
Solution Approach 2:
The patent implements a nested structure where memory cells are arranged around penetrating pillars in a compact configuration. This nested arrangement maximizes space utilization by positioning cells in the radial and vertical space surrounding each pillar, increasing cell density without requiring proportional reduction in cell size that would demand higher manufacturing precision
3Quantity of substance
If 3D stacking is implemented to increase storage density, then vertical space is utilized, but access complexity increases
Solution Approach 1:
The patent designs the penetrating pillars to serve multiple functions: they act as interconnection structures for bit lines across multiple memory layers, provide structural support for the stacked architecture, and enable radial access to memory cells at different positions. This multi-functionality reduces the need for separate access structures for each layer, thereby managing access complexity while achieving high storage density through 3D stacking
Data Source
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AI summary
Embodiments of this application provide a three-dimensional memory array, a preparation method thereof, a memory, and an electronic device, and relate to the field of storage technologies, to improve storage density of the three-dimensional memory array. The three-dimensional memory array includes a substrate, a stacked structure and a plurality of penetrating pillars. The stacked structure is disposed on the substrate, and the stacked structure includes a plurality of memory layers that are stacked in a first direction perpendicular to the substrate; the memory layer includes a plurality of word lines and a plurality of memory cells; and the memory cells are electrically connected to the word lines at a same memory layer. The penetrating pillar penetrates the stacked structure in the first direction, and the penetrating pillar includes a bit line extending in the first direction. At each memory layer, two memory cells correspond to one penetrating pillar, and the two memory cells corresponding to the penetrating pillar are disposed opposite to each other on two sides of the penetrating pillar in a second direction and are electrically connected to a bit line in the penetrating pillar; and the first direction is perpendicular to the second direction. The three-dimensional memory array may be applied to a memory and an electronic device.