3D Memory Seal Ring Layout Shared With Source and Bit Lines
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently forming seal ring structures for 3D memory devices that protect against die-stressing and contaminants like moisture, while also reducing processing resources and costs.
Innovation Solution
The seal ring structure is concurrently formed with source lines and bit lines, using the same conductive material, thereby integrating it as a one-piece structure with these components, which encloses the device and interface portions of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the seal ring structure is formed separately from source lines and bit lines, then the protection function is achieved, but the processing steps and costs increase
Solution Approach 1:
The patent combines the seal ring structure formation with the source line and bit line formation processes into a single integrated step. The seal ring structure and conductive lines are formed simultaneously using the same conductive material deposition and patterning processes, eliminating separate fabrication steps while maintaining the protective enclosure function around the device and interface portions
2Reliability
If the seal ring structure is formed separately from source lines and bit lines, then the protection function is achieved, but the processing costs increase
Solution Approach 1:
The patent merges the seal ring structure formation with the source line and bit line formation into a single process flow. Both structures are formed using the same conductive material (such as copper, cobalt, or tungsten) through identical deposition and patterning steps, eliminating the need for separate material deposition, patterning, and etching processes that would otherwise be required for a standalone seal ring structure
Solution Approach 2:
The conductive material deposition process serves multiple functions simultaneously: it forms the source lines, bit lines, and seal ring structure all in one step. This multi-functional approach reduces manufacturing complexity and cost by using a single process to create multiple essential device components with different functional roles
Data Source
AI summary
A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.