3D Memory Word Line Connection Structure With Shared Contact Vias
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Solution Overview
Problem
The challenge in three-dimensional NAND flash memory devices is to reduce the number of metal contact vias and simplify the fabrication process while maintaining the high integration level and fast access characteristics.
Innovation Solution
The solution involves conductively connecting word lines of the same height in adjacent stack structures through connection structures, allowing these word lines to share a common contact via, thereby reducing the number of contact vias and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each word line is connected to a separate contact via, then the electrical connection is reliable, but the number of contact vias increases and fabrication complexity increases
Solution Approach 1:
The patent merges multiple word lines of the same height from adjacent stack structures into a single electrical connection group. Instead of providing separate contact vias for each word line, the invention connects multiple word lines together through conductive connection portions in the connection region, allowing them to share common contact vias. This reduces the total number of contact vias and simplifies fabrication while maintaining reliable electrical connection through the merged connection structure.
Solution Approach 2:
The contact vias in the connection region are designed to serve multiple functions: they simultaneously provide electrical connection for multiple word lines of the same height from different stack structures. This multi-functional design allows a single contact via to replace what would traditionally require multiple separate contact vias, reducing overall device complexity while maintaining connection reliability.
2Ease of manufacture
If the number of contact vias is reduced, then fabrication is simplified and device size is reduced, but the electrical connection structure becomes more complex
Solution Approach 1:
The patent divides the device into distinct functional regions: device regions containing stack structures with memory cells, and connection regions containing conductive connection portions. This segmentation allows the connection structure to be optimized separately from the memory cell structure. The conductive connection portions are specifically placed in connection regions to join word lines, separating the complexity of the connection system from the simpler memory cell regions, thereby facilitating easier fabrication.
Solution Approach 2:
The patent resolves connection complexity by transitioning from vertical connections (through contact vias) to horizontal connections (through conductive connection portions in the connection region). Word lines from adjacent stacks are connected laterally through the connection region before making vertical contact to the same contact via. This dimensional shift distributes the connection complexity across the horizontal plane rather than concentrating it vertically, simplifying the overall fabrication process.
3Ease of operation
If separate contact vias are used for each word line, then the electrical connection is direct and simple, but the chip space utilization decreases
Solution Approach 1:
The patent combines multiple word line connections into shared contact vias through the conductive connection portions. By merging the electrical paths of multiple word lines of the same height, the invention reduces the total number of contact vias required, thereby freeing up chip space while maintaining complete electrical connectivity through the merged connection structure.
Data Source
AI summary
A memory device includes a substrate, a stack over the substrate, and a gate line slit extending along a first direction and dividing the stack into two portions. The stack includes a connection portion that connects the two portions of the stack. The connection portion includes at least two sub-connection portions along a second direction perpendicular to the first direction. The gate line slit includes at least two portions along the first direction. Each sub-connection portion is between adjacent two portions of the gate line slit.