3D Memory Cell Layout With Shared Wiring and Reduced Field Interference
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Solution Overview
Problem
The increasing high integration of semiconductor memory devices poses challenges in achieving efficient three-dimensional configurations, leading to issues with electric field interference and manufacturing complexity, which affect the operational speed and stability of memory cell arrays.
Innovation Solution
The semiconductor memory device incorporates a configuration with a conductive layer disposed between two conductive members, reducing wiring width and insulating layer thickness, and features a transistor structure with a conductive layer opposed to the semiconductor layer on multiple surfaces, enhancing control and reducing electric field interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration is pursued in three-dimensional configuration, then memory capacity increases, but electric field interference increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrays to a three-dimensional configuration where memory layers are stacked vertically. Multiple memory layers are arranged in the thickness direction of the substrate, allowing significant increase in memory capacity without proportionally increasing manufacturing complexity. The standardized layer structure and systematic wiring arrangement enable scalable three-dimensional integration.
Solution Approach 2:
The memory device is divided into multiple independent memory layers, each containing memory cells with transistors and capacitors. These layers are stacked vertically with insulating layers between them, allowing parallel processing and standardized manufacturing procedures to be applied to each layer, thereby managing complexity through modular segmentation.
2Area of stationary object
If wiring width is reduced for high integration, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes the thickness direction (third dimension) to arrange multiple memory layers and wiring structures. By stacking memory layers vertically and arranging bit lines and word lines in different layers, the design achieves high area efficiency while maintaining adequate wiring dimensions that are manufacturable with standard precision capabilities.
Solution Approach 2:
Different wiring structures are optimized for their specific functions: bit lines extend in the first direction through multiple memory layers, word lines extend in the second direction within memory layers, and via holes provide vertical connections. This localized optimization allows each wiring type to have appropriate dimensions and characteristics suited to its function, balancing area efficiency with manufacturing feasibility.
3Quantity of substance
If insulating layer thickness is reduced for high integration, then device density improves, but electric field interference increases
Solution Approach 1:
The patent employs insulating layers with optimized dielectric properties positioned between adjacent memory layers. These insulating layers are configured to provide sufficient electrical isolation, preventing harmful electric field interference between layers while maintaining reduced overall device thickness. The composite structure of conductive layers, semiconductor layers, and insulating layers achieves both high density and electrical isolation.
Solution Approach 2:
Insulating layers serve as intermediary structures between adjacent memory layers containing conductive members. These insulating layers act as electrical barriers that prevent direct electric field coupling between layers, enabling reduced spacing between layers (higher density) while maintaining electrical isolation through the mediating insulating material.
4Power
If transistor control is enhanced with conductive layer opposition, then ON current increases, but device complexity increases
Solution Approach 1:
The conductive layer configuration serves multiple functions simultaneously: it acts as a gate electrode controlling the semiconductor layer, provides electrical connection through via holes to upper and lower bit lines, and forms part of the memory cell structure. This multi-functionality enhances transistor control and ON current while avoiding proportional increases in device complexity through efficient structural integration.
Solution Approach 2:
The patent merges the gate electrode function with the conductive layer that connects bit lines across memory layers. The same conductive structure performs both control functions (gate electrode opposing the semiconductor layer) and connection functions (via holes to bit lines), thereby enhancing transistor performance without adding separate dedicated structures that would increase complexity.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory layers arranged in a first direction, a first via-wiring extending in the first direction, a second via-wiring in a position different from a position of the first via-wiring in a second direction and extending in the first direction. One of the plurality of memory layers includes a first wiring disposed between the first and the second via-wiring and extending in a third direction, a first semiconductor layer electrically connected to the first via-wiring, a first gate electrode opposed to the first semiconductor layer and electrically connected to the first wiring, a first memory portion electrically connected to the first semiconductor layer, a second semiconductor layer electrically connected to the second via-wiring, a second gate electrode opposed to the second semiconductor layer and electrically connected to the first wiring, and a second memory portion electrically connected to the second semiconductor layer.