3D Vertical Channel Memory Stack With Side-Contact Source Structure
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Solution Overview
Problem
Two-dimensional semiconductor devices face integration limitations due to the cost and complexity of fine pattern forming technologies, hindering the increase in data storage capacity and performance while maintaining affordable prices.
Innovation Solution
A three-dimensional semiconductor memory device with a vertical channel structure, including a stack of interlayer dielectric layers and gate electrodes, a source structure, and a mold structure, which incorporates vertical channel structures with specific layering of barrier and semiconductor patterns to enhance reliability and reduce fabrication complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited by area occupied by unit memory cell
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked in the vertical direction (third direction D3) above a common substrate, enabling data storage capacity to scale with the number of stacked layers rather than being constrained by planar area. This dimensional transition resolves the contradiction by decoupling integration capacity from lateral area occupation.
2Productivity
If fine pattern forming technology is advanced to increase integration, then data storage capacity increases, but process equipment cost increases extremely
Solution Approach 1:
Instead of increasing integration by reducing lateral pattern dimensions (which requires expensive fine pattern forming equipment), the patent increases data storage capacity by stacking memory cells vertically. The number of storage cells scales with the number of stacked layers, allowing capacity expansion without requiring advanced lateral patterning capabilities or expensive process equipment.
Solution Approach 2:
The memory device is segmented into multiple stacked layers, each containing memory cells. This segmentation allows the total storage capacity to be divided across multiple levels, with each level using standard patterning techniques. The overall capacity scales with the number of segments (layers) rather than requiring increasingly sophisticated single-layer patterning.
3Productivity
If three-dimensional vertically stacked memory cells are implemented, then integration and data storage capacity increase, but fabrication process becomes more difficult
Solution Approach 1:
The patent forms a complete stack structure (including alternating insulating layers and semiconductor layers, gate electrodes, and source/drain structures) before forming the vertical channel holes. This preliminary formation of the stacked structure simplifies subsequent processing, as the complex multi-layer architecture is already in place and only requires hole formation and filling operations, rather than requiring sequential formation of each layer with precise alignment.
Data Source
AI summary
A three-dimensional semiconductor device may include a substrate including a cell array region and a contact region, a stack structure including interlayer dielectric layers and gate electrodes, a source structure, and a mold structure between the substrate and the stack structure. First vertical channel structures are on the cell array region in vertical channel holes. Each of the first vertical channel structures may include a first barrier pattern, a data storage pattern, and a vertical semiconductor pattern, which are sequentially layered on an inner side surface of one of the vertical channel holes. The mold structure may include a first buffer insulating layer, a first semiconductor layer, a second buffer insulating layer, and a second semiconductor layer sequentially stacked on the substrate. The source structure may be in physical contact with a portion of a side surface of the vertical semiconductor pattern.