3D Memory Hook-Up Layout With Side Contacts to Cut Capacitance

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in reducing the area of the hook-up region, which increases with the number of conductive layers or semiconductor layers stacked, leading to higher electrostatic capacity and potential performance issues.

Innovation Solution

The semiconductor memory device incorporates a common hook-up region shared among multiple memory block regions, utilizing contact electrodes with a disk-shaped portion connected to the side surface of the conductive layers, which reduces the opposed area and electrostatic capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of conductive layers or semiconductor layers is increased to enhance memory capacity, then the storage capability is improved, but the area of the hook-up region increases and electrostatic capacity between adjacent layers increases

Engineering Contradiction:
Improvememory capacityVSAvoidhook-up region area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The contact electrode is designed with a disk-shaped portion that contacts the side surface of the conductive layer rather than the top surface. This side-contact configuration changes the spatial dimension of connection, allowing the hook-up region to remain compact while accommodating multiple stacked layers without proportionally increasing the hook-up area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The disk-shaped portion of the contact electrode is positioned within the lateral footprint of the conductive layer it connects to. This nested arrangement allows the contact electrode to be accommodated within the same planar space as the conductive layer, preventing the hook-up region area from increasing linearly with the number of stacked layers.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If the number of conductive layers or semiconductor layers is increased to enhance memory capacity, then the storage capability is improved, but the electrostatic capacity between adjacent layers increases

Engineering Contradiction:
Improvememory capacityVSAvoidelectrostatic capacity
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

By transitioning from top-surface contact to side-surface contact, the patent reduces the overlapping area between adjacent conductive layers in the vertical stack. The disk-shaped contact electrode contacts the side surface, minimizing the faced area between layers and thereby reducing parasitic electrostatic capacity while preserving memory capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The harmful electrostatic interaction between adjacent conductive layers is reduced by extracting the contact point from the high-capacitance top surface region and relocating it to the side surface. This separation removes the source of high electrostatic coupling while maintaining the electrical connection function.

Inventive Principle:
Principle #2Taking out (Extraction)

3Area of stationary object

If a common hook-up region is shared among multiple memory block regions, then the hook-up region area is reduced, but the wiring complexity increases

Engineering Contradiction:
Improvehook-up region areaVSAvoidwiring complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The contact electrode with a disk-shaped portion serves multiple functions: it provides electrical connection to the conductive layer, acts as a bonding pad for inter-layer connectivity, and enables sharing among multiple memory block regions. This multi-functional design allows a single hook-up region structure to serve multiple purposes, reducing overall area while managing complexity through functional integration.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250201708A1Semiconductor memory device
Publication Date: 2025.06.19 KIOXIA CORP
  • US20250201708A1 patent drawing
  • US20250201708A1 patent drawing
  • US20250201708A1 patent drawing

AI summary

A semiconductor memory device includes memory block regions arranged in a first direction, a hook-up region arranged in the first direction with respect to memory block regions, and a wiring region extending in the first direction and arranged with memory block regions and the hook-up region in a second direction. Each of memory block regions includes memory strings extending in the first direction and arranged in the second direction and a first wiring extending in the second direction and connected to memory strings in common. The wiring region includes a second wiring extending in the first direction and connected to first wirings corresponding to memory block regions in common. The hook-up region includes a third wiring connected to the second wiring and a contact electrode extending in a third direction and connected to the third wiring.