3D Memory Stack Layout for Uniform Silicon Sidewalls
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Solution Overview
Problem
Existing three-dimensional semiconductor memory devices face challenges in achieving high integration density and uniform electrical characteristics of memory cells due to non-uniform sidewall profiles of silicon patterns and word lines, which affect transistor performance.
Innovation Solution
A semiconductor device design featuring first and second pillar insulation patterns with aligned silicon patterns between them, word lines extending across these patterns without cuts, and capacitors with dielectric layers, ensuring uniform sidewall profiles and consistent electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in vertical direction to increase integration degree, then integration density is improved, but uniformity of sidewall profiles and electrical characteristics deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell layout to three-dimensional vertical stacking of memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing integration density to increase while maintaining uniform electrical characteristics through consistent formation processes applied to each layer.
Solution Approach 2:
The patent divides the memory cell structure into multiple stacked layers, with each layer containing silicon patterns, word lines, bit lines, and capacitors. This segmentation into repeating modular units allows each layer to be formed with consistent geometry, ensuring uniform sidewall profiles and electrical characteristics across the entire stacked structure.
2Ease of manufacture
If non-uniform sidewall profiles are present in silicon patterns and word lines, then manufacturing complexity is reduced, but transistor performance and electrical characteristics deteriorate
Solution Approach 1:
The patent employs controlled etching parameters and deposition conditions to achieve uniform sidewall profiles in silicon patterns and word lines. By optimizing etch selectivity, deposition temperature, and layer thickness parameters, consistent geometric dimensions are obtained throughout the stacked structure, ensuring reliable transistor performance.
Solution Approach 2:
The patent replaces mechanical or manual formation methods with precisely controlled semiconductor fabrication processes such as chemical vapor deposition, atomic layer deposition, and plasma etching. These processes provide superior control over film thickness and sidewall uniformity compared to mechanical methods, ensuring consistent electrical characteristics.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a stacked structure by alternately and repeatedly stacking insulation layers and silicon layers on a substrate; forming first openings in a vertical direction and arranged in parallel to be spaced apart in a first direction; forming second openings in the vertical direction and arranged to face the first openings in a second direction; laterally etching the silicon layer exposed by sidewalls of the first and second openings to form silicon patterns spaced apart from the substrate in the vertical direction and extending in the second direction between the first openings in the first direction and between the second openings in the first direction; filling the first and second openings and a space between the silicon patterns with an insulation layer; and forming a word line on each of upper and lower surfaces of each silicon pattern.