3D Memory Gate Stack Sidewall Roughness for Stable High Stacking
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Solution Overview
Problem
As the number of stacked memory cells in three-dimensional semiconductor memory devices increases, the stability of the manufacturing process deteriorates, leading to integration density and process stability issues.
Innovation Solution
A semiconductor memory device is designed with a source structure and a gate stacked structure, featuring a cell array region and a contact region with a stepped shape. The gate stacked structure has a higher roughness on its first sidewall in the cell array region compared to its second sidewall in the contact region, and includes a vertical structure with depressions and protrusions facing cell plugs. Additionally, a method of manufacturing involves forming a stacked structure, hole groups, and sacrificial pillars, followed by etching to create trenches and supporting holes, and finally forming a slit by coupling auxiliary holes and trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked memory cells is increased to improve integration density, then integration density is improved, but process stability deteriorates
Solution Approach 1:
The gate stacked structure is divided into two distinct regions: a cell array region with a first sidewall and a contact region with a second sidewall. This segmentation allows different surface roughness characteristics to be applied to different functional areas, enabling the structure to accommodate higher stacking while maintaining process stability through region-specific optimization.
Solution Approach 2:
The patent applies different surface roughness properties to different parts of the gate stacked structure. The first sidewall in the cell array region has a first surface roughness, while the second sidewall in the contact region has a second surface roughness. This local quality differentiation optimizes each region for its specific function, allowing increased integration density without compromising overall process stability.
2Productivity
If the number of stacked memory cells is increased to improve integration density, then integration density is improved, but manufacturing precision deteriorates
Solution Approach 1:
By segmenting the gate stacked structure into cell array and contact regions with distinct sidewalls, the patent enables independent optimization of pattern formation in each region. The first sidewall can be optimized for cell array pattern regularity while the second sidewall is optimized for contact region alignment, maintaining manufacturing precision even as stacking height increases.
Solution Approach 2:
Different surface roughness characteristics are applied locally to different sidewalls based on their functional requirements. This local quality control ensures that pattern regularity is maintained in both the cell array region and contact region, preventing manufacturing precision deterioration as integration density increases through additional stacking.
Data Source
AI summary
A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.