3D Memory Circuit Testing via Simultaneous Layer Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in efficiently testing three-dimensional (3D) memory cell arrays due to the complexity and time required for writing and reading data across multiple layers, which affects the identification and replacement of failed memory cells.
Innovation Solution
A method is introduced where data is simultaneously written to and read from each layer of a 3D memory cell array, allowing for the simultaneous performance of write and read operations across all layers, enabling the identification and replacement of failed memory cells with spare cells, thereby reducing testing time and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional sequential testing methods are used for 3D memory cell arrays, then testing thoroughness is maintained, but testing time increases significantly
Solution Approach 1:
The memory cell array is divided into multiple layers, and each layer is tested independently using separate read circuits. This segmentation allows parallel testing of different layers, reducing overall testing time while maintaining thoroughness of each individual layer's testing.
Solution Approach 2:
Multiple read circuits are combined to simultaneously perform read operations on multiple layers of the memory cell array. This merging of testing resources enables parallel processing of testing operations across different layers, significantly improving testing efficiency without compromising testing completeness.
2Productivity
If simultaneous write and read operations are performed across all layers, then testing efficiency improves, but operational complexity increases
Solution Approach 1:
The simultaneous write and read operations are segmented by layer, with each layer having dedicated control signals and read circuits. This layer-by-layer segmentation simplifies the control logic for simultaneous operations compared to a fully integrated approach, making the complex operation more manageable and implementable.
Solution Approach 2:
Write operations are performed on all layers before read operations begin, preparing the memory cells in advance. This preliminary action separates the write and read phases temporally within the simultaneous operation framework, reducing the complexity of coordinating write and read signals across multiple layers at the exact same time.
Data Source
AI summary
A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.