3D Semiconductor Memory Device Slit Insulating Layer Structure
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Solution Overview
Problem
Conventional three-dimensional non-volatile memory devices require complex processes involving pipe transistors, which are difficult to manufacture and control, and face challenges in etching memory layers with high aspect ratios, leading to potential damage and deterioration of memory cell characteristics.
Innovation Solution
A semiconductor device structure that eliminates pipe transistors by using a stack of conductive and insulating layers with a slit insulating layer, allowing for easier manufacturing and reducing source resistance, where the memory layer is formed along the inner surfaces of channel holes without needing to expose the source region, thus simplifying the etching process and preventing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipe transistors are used to couple source side and drain side memory cells, then memory cells can be connected vertically, but the number of manufacturing processes increases and threshold voltage control becomes difficult
Solution Approach 1:
The invention removes the pipe transistor component from the memory string structure. Instead of using pipe transistors to couple source and drain side memory cells, the patent uses a U-shaped channel structure where the channel layer itself provides the coupling path, eliminating the need for separate pipe transistor formation processes and simplifying manufacturing
Solution Approach 2:
The invention merges the channel coupling function with the channel layer structure itself. The U-shaped channel layer directly couples source and drain side memory cells without requiring separate pipe transistor components, combining multiple functions into a single integrated structure
2Productivity
If memory layer is formed along inner surfaces of channel holes with high aspect ratios, then vertical memory strings can be created, but etching the memory layer becomes difficult and damage to the memory layer may occur
Solution Approach 1:
The invention segments the memory layer formation process by first forming the memory layer along the inner surfaces of channel holes, then selectively removing portions of the memory layer at specific locations (such as at the bottom of channel holes or in sacrificial regions) to expose source regions or create desired patterns, thereby enabling controlled access without damaging the overall memory layer structure
Solution Approach 2:
The invention performs preliminary actions by forming sacrificial layers or protective structures before forming the memory layer, which facilitate subsequent selective removal processes. These preliminary structures guide the etching process and protect critical memory layer regions from damage during manufacturing
Data Source
AI summary
Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit 5 insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.