3D Memory Stack Slit Structure for Shorter IC Interconnects
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Solution Overview
Problem
Wires in integrated circuits (ICs) dominate performance, functionality, and power consumption as they degrade with scaling, necessitating improved 3D stacking techniques to reduce wire lengths and enhance transistor placement.
Innovation Solution
The development of multilayer 3D IC devices with layer transfer technologies that support the reuse of donor wafers and fabrication of active devices on transferred layers, incorporating slits for gate replacement and self-aligned transistors, enabling independent memory units and cache memory with refresh circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If 3D stacking is implemented to reduce wire lengths, then wire performance degrades are reduced and transistor placement is improved, but device complexity increases due to multiple fabrication techniques required
Solution Approach 1:
The fabrication process is segmented into distinct modules: forming sacrificial structures in first regions, forming active devices in second regions, selectively removing sacrificial structures, and transferring layers. This segmentation allows complex 3D integration to be broken down into manageable steps, reducing overall fabrication complexity while achieving short wire lengths through vertical stacking.
Solution Approach 2:
The patent transitions from planar 2D integration to three-dimensional stacking by forming active devices on transferred layers above existing structures. This dimensional change enables transistors to be placed closer together vertically, significantly reducing wire lengths and improving signal integrity while managing the added fabrication complexity through systematic process division.
2Manufacturing precision
If layer transfer technology is used to enable 3D stacking, then transistor placement precision is improved, but manufacturing complexity increases
Solution Approach 1:
Sacrificial structures are formed in advance in first regions before active devices are created in second regions. These sacrificial structures serve as temporary placeholders that enable precise alignment and transfer of active device layers, achieving high transistor placement precision while managing process complexity through preparatory steps.
Solution Approach 2:
Sacrificial structures act as intermediary elements during the fabrication process, facilitating the transfer of active devices to precise locations. These temporary structures enable controlled layer transfer and alignment, improving manufacturing precision while the systematic use of intermediaries helps manage overall process complexity.
3Reliability
If multiple layers are stacked to increase functionality, then IC performance is improved, but power consumption increases due to wire dominance
Solution Approach 1:
By stacking multiple layers vertically, the patent reduces the lateral distance that signals must travel through wires, thereby reducing wire dominance in performance and power consumption. The vertical arrangement allows transistors to be placed closer together, shortening interconnect paths and reducing the energy required for signal transmission while maintaining high IC performance.
Solution Approach 2:
The segmentation of fabrication processes enables precise control over layer formation and interconnect creation, allowing optimization of wire lengths and routing paths. This segmented approach facilitates better power management by reducing the total wire length and improving signal integrity across multiple stacked layers.
Data Source
AI summary
A semiconductor device including: a first level including memory control circuits (include a plurality of refresh circuits for the memory units) which include first transistors; a second level including a first array of memory cells including second transistors self-aligned to at least one of the third transistors; a third level disposed on top of the second level disposed on top of first level, the third level including a second array of memory cells including third transistors; a fourth level disposed on top of the third level, the fourth level including a third array of memory cells including fourth transistors, second level is bonded to the first level, a plurality of slits disposed through the second level, the third level, and the fourth level, the slits enable gate replacement of a plurality of the third transistors, where the second array of memory cells include a plurality of independently controlled memory units.