3D Memory Gate Line Slit Layout for Leakage Prevention
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Solution Overview
Problem
Existing 3D NAND memory devices face challenges with gate line slit structure tilting due to stress gradients at the core/staircase transition area, leading to leakage issues between word lines and array common source, which reduces yield significantly.
Innovation Solution
A method for forming a 3D memory device with a gate line slit structure that includes a narrow portion with a reduced width at the transition area between the core and staircase regions, ensuring a minimum distance between the gate line slit and adjacent channel structures to prevent tilting and leakage, involving the formation of an alternating dielectric stack, channel structures, and conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate line slit structure is formed with uniform width through the alternating dielectric stack, then the fabrication process is simple, but stress gradients at the core/staircase transition area cause tilting of the gate line slit structure leading to leakage between word lines and array common source
Solution Approach 1:
The gate line slit structure is designed with different widths at different locations: a first width in the core region and a second (narrower) width at the core/staircase transition area. This local variation in geometry allows the structure to better withstand stress gradients at the transition area, preventing tilting and leakage while maintaining overall fabrication feasibility through selective width control.
2Area of stationary object
If the gate line slit structure is formed closer to channel structures to increase density, then area utilization improves, but stress-induced tilting increases the risk of leakage between word lines and array common source
Solution Approach 1:
The gate line slit structure employs location-dependent width: a narrower second width at the stress-prone core/staircase transition area and a wider first width in the core region. This allows the structure to maintain adequate spacing from channel structures at the transition area to prevent leakage, while maximizing area utilization in the core region where stress is less problematic.
3Reliability
If the gate line slit structure is formed with reduced width at the transition area, then tilting and leakage are prevented, but the fabrication precision requirements increase
Solution Approach 1:
The gate line slit structure is segmented into distinct width regions: a first width region in the core area and a second (narrower) width region at the core/staircase transition area. This segmentation allows independent optimization of each region's dimensions, with the narrower segment specifically targeting the transition area to prevent leakage while the wider segment maintains ease of fabrication in the core region.
Data Source
AI summary
A method for forming a 3D memory device is disclosed. The method includes forming an alternating dielectric stack on a substrate. Then a plurality of channel structures and dummy channel structures vertically penetrating the alternating dielectric stack are formed, The channel structures are located in a core region, and the dummy channel structures are located in a staircase region. A gate line silt structure is formed vertically penetrating the alternating dielectric stack and laterally extending in a first direction. The gate line silt structure includes a narrow portion that has a reduced width along a second direction different from the first direction.