3D Memory Slit Structure for Stable High-Aspect-Ratio Stacks
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Solution Overview
Problem
The integration density of two-dimensional non-volatile memory devices is limited, leading to the development of three-dimensional non-volatile memory devices with stacked memory cells, which require improved structural stability and manufacturing methods to enhance operational reliability.
Innovation Solution
A semiconductor device with a stacked structure featuring alternating conductive and insulating layers, sacrificial layers, and slit structures with through portions and protrusions to separate regions, along with a contact plug for electrical connection, and a manufacturing method that forms these structures to achieve a stabilized and high-aspect-ratio slit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional non-volatile memory devices are used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with each layer containing memory cells formed over the substrate. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate rather than only the horizontal plane.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically. Each layer contains sacrificial layers, insulating layers, and conductive layers that are segmented and repeated across different heights. This segmentation allows independent formation and optimization of each layer while achieving high overall integration density.
2Quantity of substance
If three-dimensional stacked memory cells are implemented, then integration density increases, but structural stability deteriorates
Solution Approach 1:
Interlayer insulating layers are formed between adjacent memory cell layers to provide mechanical cushioning and stress relief. These insulating layers prevent direct contact between stacked conductive layers, reducing stress concentration and preventing structural failure. The cushioning effect maintains structural stability while enabling the high-density stacked configuration.
Solution Approach 2:
The patent employs composite material structures combining different materials with complementary properties. Sacrificial layers (e.g., silicon oxide) and insulating layers (e.g., silicon nitride) are alternately stacked with conductive layers. This composite structure provides both mechanical strength for stability and the necessary functional properties for memory operation.
3Quantity of substance
If three-dimensional stacked memory cells are implemented, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
Sacrificial layers are formed first in each memory cell layer before forming the conductive layers. These sacrificial layers serve as preliminary structural templates and alignment references. By establishing the sacrificial layer pattern first, subsequent conductive layer formation can be precisely aligned to the underlying structure, maintaining manufacturing precision across multiple stacked layers.
Solution Approach 2:
Interlayer insulating layers act as intermediary structures between adjacent memory cell layers. These insulating layers provide a buffer zone that facilitates precise alignment and formation of conductive layers in upper layers relative to lower layers. The intermediary insulating layers enable controlled deposition and patterning processes to maintain precision across the vertical stack.
Data Source
AI summary
A semiconductor device includes a stacked structure including a first region in which conductive layers and the insulating layers are stacked alternately with each other, and a second region in which sacrificial layers and the insulating layers are stacked alternately with each other, a first slit structure located at a boundary between the first region and the second region and including a first through portion passing through the stacked structure and first protrusions extending from a sidewall of the first through portion, a second slit structure located at the boundary and including a second through portion passing through the stacked structure and second protrusions extending from a sidewall of the second through portion and coupled to the first protrusions, a circuit located under the stacked structure, and a contact plug passing through the second region of the stacked structure and electrically connected to the circuit.