3D Memory Semiconductor Structure With Aluminum Soldering Contacts
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Solution Overview
Problem
3D semiconductor memories face high complexity and cost due to the special requirements of conductive via structures and solder pads, which complicate the manufacturing process.
Innovation Solution
A semiconductor structure with a stack structure, channel structure, and soldering structures that include a first and second portion with specific size ratios, using aluminum as material, and an isolating structure to simplify the process and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tungsten-filled contact structures and special conductive via structures are used to meet the requirements of 3D memory, then the reliability and electrical performance are improved, but the device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent replaces expensive tungsten-filled contact structures with aluminum-based soldering structures that can be formed using standard CMOS-compatible processes. The aluminum material is less expensive and allows for simpler fabrication, achieving the same electrical connection function without the complexity of tungsten deposition and filling processes.
Solution Approach 2:
The patent changes the material parameter from tungsten to aluminum, and modifies the geometric parameters of the contact structures by introducing specific size ratios (first portion and second portion with defined dimensional relationships). These parameter changes enable the structures to be formed using standard semiconductor manufacturing processes while maintaining electrical performance.
2Reliability
If multiple specialized conductive via structures and solder pads with specific material requirements are implemented, then the electrical connectivity and signal integrity are improved, but the manufacturing process complexity and production cost increase
Solution Approach 1:
The patent designs the soldering structure to serve multiple functions: it acts as a contact structure, a via structure, and a solder pad simultaneously. The aluminum-based structure can be formed using the same deposition and patterning processes as standard interconnect layers, eliminating the need for separate specialized processing steps for different conductive elements.
Solution Approach 2:
The patent merges the functions of separate contact structures, via structures, and solder pads into a unified aluminum-based soldering structure. This consolidation allows all these elements to be formed in the same process step using standard CMOS-compatible aluminum deposition, significantly simplifying the manufacturing process.
3Ease of manufacture
If standard CMOS-compatible processes are used for forming contact structures, then the manufacturing cost and process complexity are reduced, but the ability to meet special electrical performance requirements deteriorates
Solution Approach 1:
The patent modifies the geometric parameters of the aluminum contact structures, specifically defining relationships between the dimensions of the first portion and second portion. These parameter optimizations ensure that the standard CMOS-compatible aluminum structures achieve the same electrical performance characteristics as specialized tungsten structures, including resistance and current carrying capacity.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
The present disclosure relates to a semiconductor structure, a forming method thereof and a semiconductor device. The semiconductor structure includes: a stack structure; a semiconductor layer on the stack structure; a channel structure extending through the stack structure and into the semiconductor layer; a contact structure extending along a stacking direction of the stack structure; and a first soldering structure and a second soldering structure, wherein the first soldering structure penetrates through the semiconductor layer and is connected with the contact structure and the second soldering structure is connected with the semiconductor layer.