3D Memory Cell Chip Bonding With Source Resistance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration density of two-dimensional non-volatile memory devices is limited, necessitating the development of three-dimensional structures, and existing manufacturing methods for these devices face challenges in improving operational reliability and efficiency.
Innovation Solution
A method involving the formation of a cell chip with a source layer and stacked structure, flipping the chip to expose the source layer for surface treatment, and bonding it to a peripheral circuit chip, which includes reducing the source layer resistance through laser irradiation or dopant implantation, thereby enhancing the manufacturing process and device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional non-volatile memory device structure is used, then manufacturing process is simple, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional memory structure to a three-dimensional structure by stacking multiple layers (tunnel insulating layer, charge blocking layer, data storage layer, and barrier layer) vertically over the channel layer. This vertical stacking enables higher integration density by utilizing the third dimension (height) rather than only expanding in the planar direction.
2Reliability
If conventional manufacturing method is used, then process steps are established, but operational reliability is insufficient
Solution Approach 1:
The patent performs preliminary actions during manufacturing by forming specific layer structures (tunnel insulating layer, charge blocking layer, data storage layer, barrier layer) with controlled thicknesses and materials before final device operation. The source layer is also prepared with specific doping concentrations and thicknesses in advance to ensure reliable charge trapping and retention characteristics.
Solution Approach 2:
The patent optimizes operational reliability by carefully controlling physical parameters including layer thicknesses (tunnel insulating layer: 5-15nm, charge blocking layer: 5-20nm, data storage layer: 10-30nm, barrier layer: 5-15nm), doping concentrations in the source layer, and material compositions. These parameter optimizations ensure proper charge injection, trapping, and retention while maintaining manufacturability.
3Productivity
If source layer resistance is high, then manufacturing is easier, but device operation efficiency is poor
Solution Approach 1:
The patent controls source layer resistance by optimizing doping concentration (1×10^19 to 1×10^21 atoms/cm³) and thickness (5nm to 20nm) parameters. By adjusting these parameters, the source layer achieves appropriate resistance levels that balance efficient charge injection during operation with manufacturability constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method simplifies the manufacturing process, reduces source layer resistance, and improves the operational reliability and integration density of three-dimensional non-volatile memory devices.
Implementation Method 1
irradiating the source layer with a laser beam incident on the rear surface of the source layer
Implementation Method 2
performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.