3D Memory Source Contact to Vertical Channel Bottom

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Solution Overview

Problem

Current three-dimensional memory devices face challenges in achieving enhanced source contact between replacement source contact layers and vertical semiconductor channels, leading to increased contact resistance and reduced performance.

Innovation Solution

A three-dimensional memory device is designed with a source contact layer formed over a substrate, featuring an alternating stack of insulating and electrically conductive layers, and dielectric pillar structures embedded within the substrate, providing structural support and enhanced contact between the source contact layer and vertical semiconductor channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a replacement source contact layer is formed in conventional three-dimensional memory devices, then the source contact can be updated or modified, but the contact resistance increases and performance deteriorates due to insufficient contact area with vertical semiconductor channels

Engineering Contradiction:
Improvesource contact resistanceVSAvoidcontact area between source contact layer and vertical semiconductor channels
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a conventional planar contact interface to a three-dimensional contact architecture where the source contact layer wraps around and contacts the bottom surfaces of vertical semiconductor channels. This dimensional change increases the contact area from a two-dimensional plane to a multi-faceted three-dimensional interface, thereby reducing contact resistance while maintaining the replacement source contact functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The source contact layer is positioned within and around the vertical semiconductor channels, creating a nested structure where the contact layer is embedded in the channel architecture. This nesting arrangement maximizes the contact area between the source contact layer and the channels, allowing for improved electrical contact while maintaining compact device geometry.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the contact area between source contact layer and vertical semiconductor channels is increased to reduce contact resistance, then the device structure becomes more complex

Engineering Contradiction:
Improvesource contact resistanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source contact layer is divided into multiple segments or regions that can be independently formed and positioned around different vertical semiconductor channels. This segmentation allows for modular fabrication processes and simplifies the overall manufacturing complexity while achieving comprehensive contact coverage across all channels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The source contact layer serves multiple functions simultaneously: it provides electrical contact to the vertical semiconductor channels, acts as a replacement contact structure, and maintains structural integrity of the device. This multi-functionality reduces the need for additional separate components, thereby managing device complexity while achieving improved contact performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10559582B2Three-dimensional memory device containing source contact to bottom of vertical channels and method of making the same
Publication Date: 2020.02.11 SANDISK TECHNOLOGIES LLC
  • US10559582B2 patent drawing
  • US10559582B2 patent drawing
  • US10559582B2 patent drawing

AI summary

A three-dimensional memory device includes source-level material layers located over a substrate, the source-level material layers containing a source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the substrate-level material layers, memory stack structures extending through the alternating stack, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel having a bottom surface that contacts a respective horizontal surface of the source contact layer, and dielectric pillar structures embedded within the substrate-level material layers and located between the memory stack structures.