3D Memory Source Structure With Mixed Crystal Regions
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Solution Overview
Problem
Existing semiconductor memory devices face performance degradation due to drain saturation current issues and length discrepancies during the removal of gate dielectric layers, particularly in three-dimensional memory cell structures.
Innovation Solution
The semiconductor memory device incorporates a stacked structure with alternating gate electrodes and interlayer insulating layers, featuring channel structures with core insulators and channel layers, and a source structure with distinct crystal structures to mitigate these issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used to increase data storage capacity, then storage capacity is improved, but drain saturation current performance degrades
Solution Approach 1:
The source structure is divided into multiple source regions (first source region, second source region, third source region) with different crystal orientations. This segmentation allows each region to contribute differently to carrier transport, improving drain saturation current while maintaining high storage capacity through the 3D vertical channel structure.
Solution Approach 2:
Different regions of the source structure are given different local properties through varied crystal orientations. The first source region has a different crystal orientation than the second and third source regions, creating localized quality variations that optimize carrier injection and transport in specific areas, thereby improving overall device performance.
2Ease of manufacture
If gate dielectric layer is removed during processing, then manufacturing progress is achieved, but length discrepancy occurs in vertical direction
Solution Approach 1:
The gate dielectric layer is configured to extend beyond the gate electrode in the vertical direction before removal. This preliminary extension ensures that when the gate dielectric is subsequently removed, the underlying structures maintain uniform length and alignment, preventing manufacturing defects caused by length discrepancies.
Solution Approach 2:
The gate dielectric layer serves as an intermediary structure during processing. Its extended configuration acts as a temporary reference or mask that guides subsequent processing steps, ensuring uniform removal and preventing length variations in the final structure.
3Reliability
If source structure with different crystal structures is implemented, then drain saturation current performance is improved, but device complexity increases
Solution Approach 1:
The source structure is segmented into multiple regions with different crystal orientations, where each segment serves a specific function in carrier transport. This segmentation improves performance by optimizing local carrier injection while the modular nature of the segments helps manage the overall complexity through systematic design.
Data Source
AI summary
A semiconductor memory device includes a stacked structure comprising gate electrodes and interlayer insulating layers that are alternately stacked; a source structure on the stacked structure; and channel structures extending in the stacked. Each of the channel structures includes a core insulator that extends in the stacked structure in the vertical direction, wherein the core insulator protrudes into the source structure; a channel layer extending around the core insulator; and a gate dielectric layer extending around at least a portion of the channel layer, wherein a portion of the gate dielectric layer extends in a horizontal direction on the stacked structure. The source structure includes a first source part that is in contact with the channel structures and second source parts spaced apart from the channel structures by the first source part, wherein the first source part has a different crystal structure from the second source parts.