3D Memory Device Source-Side Select Gate Isolation
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently isolating and arranging source layers and select gate electrodes to enhance memory performance and scalability.
Innovation Solution
A three-dimensional memory device design featuring alternating stacks of insulating and conductive layers with laterally spaced source layers and source-side select gate electrodes, where the source-side select gate electrodes are isolated by dielectric structures, and the conductive layers are formed to contact backside trench fill structures, enabling precise electrical isolation and contact configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source layers are closely arranged to increase memory density, then productivity is improved, but electrical isolation between source layers deteriorates
Solution Approach 1:
Dielectric isolation structures are introduced as intermediary elements between adjacent source layers and select gate electrodes. These dielectric structures physically separate the conductive elements, preventing electrical leakage while allowing the source layers to be closely spaced for high density. The dielectric material acts as a mediator that enables close proximity arrangement without compromising electrical isolation.
2Loss of energy
If source-side select gate electrodes are positioned close to source layers to reduce capacitance, then loss of energy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The select gate structure is segmented into multiple portions: source-side select gate electrodes positioned close to source layers for low capacitance, and drain-side select gate electrodes positioned at the opposite end. This segmentation allows each electrode group to be optimized for its specific function while maintaining overall device performance. The segmented approach reduces the need for high precision across the entire gate structure.
3Reliability
If alternating stacks of insulating and conductive layers are used to improve electrical isolation, then reliability is improved, but device complexity increases
Solution Approach 1:
Multiple functional layers are merged into a single alternating stack structure where insulating layers provide both electrical isolation and structural support, while conductive layers serve as word lines and select gates. This merging approach achieves comprehensive electrical isolation without proportionally increasing device complexity, as the same layers perform multiple functions simultaneously.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer.