3D Memory Source Structure With Discontinuous Interface for Density
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Solution Overview
Problem
Existing two-dimensional semiconductor devices face limitations in integration density due to the need for high-priced apparatuses to form fine patterns, limiting their scalability and efficiency.
Innovation Solution
A three-dimensional semiconductor memory device with improved reliability and integration density, the device includes a source structure with sequentially stacked conductive patterns and vertically stacked electrodes, featuring a discontinuous interface and different crystal structures in the conductive patterns, enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor devices are used to achieve fine patterns, then manufacturing precision is improved, but device complexity and manufacturing cost increase due to high-priced apparatuses
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked structures. By stacking multiple source conductive patterns and electrode structures in the vertical direction, the device achieves higher integration density without requiring increasingly complex fine pattern formation apparatuses, thus resolving the contradiction between manufacturing precision and device complexity
Solution Approach 2:
The source structure is divided into multiple discrete source conductive patterns (first, second, third source conductive patterns) stacked vertically, each with specific crystal orientations. This segmentation allows each layer to be formed with controlled crystal structures, achieving fine pattern precision through modular construction rather than requiring single-step high-precision patterning
2Quantity of substance
If two-dimensional semiconductor devices are used to increase integration density, then area utilization is improved, but reliability deteriorates due to limited scalability
Solution Approach 1:
The patent increases integration density by extending the device architecture into the vertical dimension with stacked source conductive patterns and electrode structures. This three-dimensional configuration provides scalable reliability because each vertical stack operates as an independent functional unit, allowing error isolation and redundancy implementation without compromising the integrity of the entire device
Solution Approach 2:
Different source conductive patterns are assigned different crystal structures (e.g., first source conductive pattern with first crystal structure, second source conductive pattern with second crystal structure). This local differentiation optimizes the electrical properties and reliability of specific regions within the device, allowing tailored performance characteristics for different functional requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D semiconductor memory device achieves improved integration density and reliability by utilizing a source structure with stacked conductive patterns and electrodes, enabling efficient data storage and erasure through a gate-induced drain leakage current.
Implementation Method 1
enabling efficient data storage and erasure through a gate-induced drain leakage current
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.