3D Memory Source-Layer Segmentation for Electrical Isolation
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in efficiently isolating and integrating source lines, leading to performance limitations and manufacturing complexities.
Innovation Solution
The integration of laterally spaced apart source layers and source-side select gate electrodes, separated by dielectric isolation structures, within a three-dimensional memory device, along with a method of forming these components through alternating stacks and selective patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source lines are integrated in conventional three-dimensional memory devices, then device functionality is achieved, but electrical isolation between source lines becomes difficult and manufacturing complexity increases
Solution Approach 1:
The source lines are segmented into discrete source layers that are laterally spaced apart and electrically isolated from each other by dielectric material. This segmentation allows each source line to be independently controlled and isolated, resolving the contradiction between achieving device functionality and maintaining electrical isolation.
Solution Approach 2:
The patent transitions from planar source line integration to vertical stacking of alternating conductive and insulating layers. By utilizing the vertical dimension, source lines are separated in the vertical direction while maintaining lateral spacing, thereby achieving electrical isolation without increasing manufacturing complexity.
2Productivity
If source layers are laterally spaced apart and electrically isolated, then electrical isolation and performance are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent combines multiple functions into a single alternating stack structure that simultaneously provides word lines, source lines, select gate electrodes, and dielectric isolation. This merging of functions into a unified structure simplifies the manufacturing process by reducing the number of separate fabrication steps required.
Solution Approach 2:
The dielectric isolation structures are formed between source layers during the alternating stack fabrication process itself, rather than as a separate subsequent step. This preliminary action integrates isolation into the main manufacturing flow, improving productivity without significantly increasing process complexity.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.