3D Memory Source Rails Using Sacrificial Groove Replacement
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in efficiently forming source rails that support vertical NAND strings, particularly in maintaining structural integrity and electrical connectivity.
Innovation Solution
A method involving the formation of sacrificial source-level rails followed by replacement with doped semiconductor source rails, integrated within an alternating stack of insulating and conductive layers, to create a stable and functional source-level structure for three-dimensional memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If sacrificial rails are used to form source rails, then the structural integrity during manufacturing is improved, but additional manufacturing steps and process complexity are introduced
Solution Approach 1:
Sacrificial rails are formed in advance during the manufacturing process to provide structural support before the actual source rails are created. The sacrificial rails serve as temporary structures that maintain structural integrity during subsequent processing steps, and are removed later to reveal the final source rail structure.
Solution Approach 2:
The sacrificial rails act as intermediary structures that facilitate the manufacturing process. They provide the necessary structural framework during fabrication and are subsequently removed, having served their purpose as temporary mediators between the manufacturing process and the final device structure.
2Reliability
If doped semiconductor source rails are formed, then electrical connectivity is improved, but doping process complexity and manufacturing difficulty increase
Solution Approach 1:
The semiconductor material is doped to change its electrical parameters, transforming it from an electrically inactive or poorly conductive state to a highly conductive state suitable for source rail functionality. This parameter change enables the material to serve as an effective electrical conductor while maintaining structural integrity.
3Reliability
If source rails are laterally spaced apart, then individual memory element operation is improved, but the area occupied by source rails increases
Solution Approach 1:
The source rails are arranged in a lateral configuration rather than a vertical stack, allowing memory elements to be positioned between the rails. This dimensional arrangement enables individual memory element operation while optimizing the use of available space on the substrate.
Data Source
AI summary
A three-dimensional memory device includes a source-level structure located over a substrate, an alternating stack of insulating layers and electrically conductive layers located over the source-level structure, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings. The source-level structure includes a lower source-level semiconductor layer including elongated grooves in an upper portion thereof, doped semiconductor source rails located within the elongated grooves, and an upper source-level semiconductor layer. The doped semiconductor source rails are laterally spaced apart from each other along a first horizontal direction and laterally extend along a second horizontal direction. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel that contacts a respective one of the doped semiconductor source rails.