3D Memory Stack Source Structure Using Sacrificial Layer Openings

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Solution Overview

Problem

The existing three-dimensional non-volatile memory elements face challenges in achieving stable and reliable operation due to limitations in their structure and manufacturing processes, which affect the integration density and operational characteristics.

Innovation Solution

A semiconductor device is designed with a specific structure that includes a first source layer with varying thickness portions, a stack of conductive and insulating layers, and a channel structure passing through the stack, along with a slit extending to the second portion of the sacrificial layer, allowing for improved stability and reduced manufacturing complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If three-dimensional non-volatile memory elements are designed with vertically stacked memory cells to improve integration density, then the integration density is improved, but the structural stability and operational reliability deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoidoperational reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory device is divided into multiple discrete components including alternating conductive layers and insulating layers, with channel structures segmented through slits. This segmentation allows each layer to be optimized independently while maintaining overall structural integrity and reliability in the vertically stacked configuration

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a nested structure where channel structures are positioned within alternating conductive and insulating layers, with slits providing access through the stacked layers. This nested arrangement enables high integration density while maintaining structural stability through the hierarchical organization of components

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If complex manufacturing processes are used to achieve stable structure and improved reliability, then the reliability is improved, but the manufacturing complexity and cost increase

Engineering Contradiction:
Improveoperational reliabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Sacrificial layers are formed in advance at specific positions before the main stacking process. These pre-positioned sacrificial layers facilitate subsequent formation of slits and channel structures, simplifying the overall manufacturing process while ensuring structural reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Sacrificial layers serve as intermediary elements during manufacturing, enabling the formation of slits and channel structures without requiring complex direct etching or patterning of the final structures. These intermediaries are removed after serving their purpose, simplifying the manufacturing process

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12178042B2Semiconductor device and a method of manufacturing a semiconductor device
Publication Date: 2024.12.24 SK HYNIX INC
  • US12178042B2 patent drawing
  • US12178042B2 patent drawing
  • US12178042B2 patent drawing

AI summary

A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.